Patents by Inventor Chun-Yi Lu

Chun-Yi Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Patent number: 10930769
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10916694
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Tai-Cheng Hou, Wei-Xin Gao, Fu-Yu Tsai, Chin-Yang Hsieh, Chen-Yi Weng, Jing-Yin Jhang, Bin-Siang Tsai, Kun-Ju Li, Chih-Yueh Li, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Yu-Tsung Lai, Wei-Hao Huang
  • Publication number: 20210005734
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH
  • Patent number: 10879221
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin
  • Publication number: 20200400917
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU, Ming-Ta CHOU
  • Patent number: 10866384
    Abstract: A lens assembly driving apparatus includes a holder, a metal yoke, a carrier, a lens assembly, a magnet set, a coil and at least one elastic element. The metal yoke is coupled with the holder. The carrier is movably disposed in the metal yoke. The carrier includes an object-side portion and at least three inner surfaces. The object-side portion has an object-side central hole. The lens assembly has an optical axis. The optical axis is corresponding to the object-side central hole. The lens assembly is coupled in the carrier. A movement of the lens assembly relative to the holder is according to a movement of the carrier. The magnet set includes only two magnets. The coil surrounds and is fixed at an exterior of the carrier. The elastic element is coupled with the carrier and the holder.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 15, 2020
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Ming-Ta Chou
  • Publication number: 20200370184
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Publication number: 20200365682
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Publication number: 20200365569
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin
  • Publication number: 20200358873
    Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Patent number: 10818562
    Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 10811367
    Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 20, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
  • Patent number: 10802243
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 13, 2020
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Wen-Hung Hsu, Ming-Ta Chou
  • Patent number: 10788854
    Abstract: A clamshell electronic device is provided. The clamshell electronic device includes a device body, a cover, an auxiliary display unit and an orientation adjustment mechanism. The cover pivots on the device body, and the cover includes a cover notch. The auxiliary display unit is disposed on the device body, wherein the auxiliary display unit is adapted to be rotated between a first unit orientation and a second unit orientation. The orientation adjustment mechanism is connected to the cover and the auxiliary display unit, wherein when the cover is in a first cover orientation relative to the device body, the cover covers the device body, and the auxiliary display unit is in the first unit orientation and corresponds to the cover notch. The user can obtain information such as time, weather or messages directly via the auxiliary display unit in the the cover notch.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 29, 2020
    Assignee: WISTRON CORP.
    Inventors: Chen Yi Liang, Chen-Wen Liu, Ming-Ju Hsieh, Tzu Yuan Tseng, Chun Yi Lu, Ko-Chen Chang
  • Patent number: 10784362
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Carlos H. Diaz, Chih-Sheng Chang, Cheng-Yi Peng, Ling-Yen Yeh
  • Patent number: 10774427
    Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 15, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Yi Wu, Chun-Hung Lu
  • Publication number: 20200285273
    Abstract: A clamshell electronic device is provided. The clamshell electronic device includes a device body, a cover, an auxiliary display unit and an orientation adjustment mechanism. The cover pivots on the device body, and the cover includes a cover notch. The auxiliary display unit is disposed on the device body, wherein the auxiliary display unit is adapted to be rotated between a first unit orientation and a second unit orientation. The orientation adjustment mechanism is connected to the cover and the auxiliary display unit, wherein when the cover is in a first cover orientation relative to the device body, the cover covers the device body, and the auxiliary display unit is in the first unit orientation and corresponds to the cover notch.
    Type: Application
    Filed: July 24, 2019
    Publication date: September 10, 2020
    Inventors: Chen Yi LIANG, Che-Wen LIU, Ming-Ju HSIEH, Tzu Yuan TSENG, Chun Yi LU, Ko-Chen CHANG
  • Publication number: 20200271945
    Abstract: A lens driving module includes a holder, a cover, a carrier, at least one first magnet, a first coil, at least two second magnets, at least one first sensor and at least one second sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover and for coupling to a lens. The first magnet is movably disposed in the cover. The first coil is wound around an outer side of the carrier. The second magnets are disposed on one end of the carrier. The first sensor is for detecting a magnetic field of the second magnets. The second sensor is for detecting a magnetic field of the first magnet.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU
  • Publication number: 20200258802
    Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh