Abstract: A method of forming a polycide-to-polysilicon capacitor simultaneously with a CMOS device with polycide gate is described. Field oxide regions, n-well and p-well regions, and gate oxide regions are formed in and on a silicon substrate. A first layer of polysilicon, having a suitable doping concentration, is formed on the surface of the substrate and the field oxide regions. A layer of silicide is formed over the layer of polysilicon. The layer of silicide is ion implanted in a vertical direction to produce the low voltage coefficient and high linearity. A layer of interpoly oxide is formed over the layer of silicide. The layer of interpoly oxide is densified. A second layer of polysilicon is formed on the surface of the interpoly oxide. The second layer of polysilicon is doped, and then patterned to form the top plate of the capacitor. The layer of interpoly oxide is removed, except in the area under the top plate of the capacitor, where it acts as a capacitor dielectric.