Patents by Inventor Chun-Yi Shih

Chun-Yi Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150009154
    Abstract: An electronic device, adapted for interacting with a stylus, wherein the stylus transmits a control signal to the electronic device, is provided. The electronic device includes a touch screen, a communicating unit and a processing unit. The touch screen receives a touch action made by the stylus. The communicating unit receives the control signal transmitted by the stylus. The processing unit is coupled to the touch screen and the communicating unit, receives the touch action and the control signal. The processing unit determines a touch gesture corresponding to a touch action according to the touch action, and determines an operating state of the stylus according to the control signal. Also, the processing unit executes a corresponding action according to the touch gesture, the operating state and/or an application program which is currently executed by the electronic device.
    Type: Application
    Filed: October 24, 2013
    Publication date: January 8, 2015
    Applicant: Acer Incorporated
    Inventors: Chun-Yi Shih, Yi-Wen Liu
  • Patent number: 5846860
    Abstract: A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: December 8, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Shih, Julie Huang, Mong-Song Liang
  • Patent number: 5804488
    Abstract: A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: September 8, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi Shih, Shun-Liang Hsu, Jyh-Kang Ting
  • Patent number: 5654231
    Abstract: A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away where they are not covered by a buried contact mask to provide an opening to the semiconductor substrate. Ions are implanted through the opening into the semiconductor substrate to form a buried contact junction. A layer of dielectric material is deposited over the first polysilicon layer and over the semiconductor substrate within the opening. The layer is anisotropically etched to leave spacers on the sidewalls of the first polysilicon layer and adjacent the opening. A second layer of polysilicon is deposited overlying the first polysilicon layer and over the substrate within the opening.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: August 5, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Jin-Yuan Lee, Chun-Yi Shih
  • Patent number: 5554558
    Abstract: A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: September 10, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shun-Liang Hsu, Jyh-Kang Ting, Chun-Yi Shih
  • Patent number: 5451529
    Abstract: A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: September 19, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shun-Liang Hsu, Chun-Yi Shih