Abstract: A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.

Abstract: A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.

Abstract: A non-volatile memory device and an error compensation method for verifying the same are provided. The non-volatile memory device includes a memory block, a word line driver, a bit line circuit and a controller. The memory block includes multiple memory cells. After a first programming process and a first verification process are performed on the memory cells, the controller performs reverse reading to the control terminals of the memory cells, applies a preset voltage to the control terminals of the memory cells according to preset programming data by using the word line driver, reads data from the memory cells by using the bit line circuit, and determines whether the data of each memory cell is normal according to the data read from the memory cells. When the data of specific memory cells is not normal, the controller performs a second programming process to the specific memory cells.

Abstract: A non-volatile memory device and an error compensation method for verifying the same are provided. The non-volatile memory device includes a memory block, a word line driver, a bit line circuit and a controller. The memory block includes multiple memory cells. After a first programming process and a first verification process are performed on the memory cells, the controller performs reverse reading to the control terminals of the memory cells, applies a preset voltage to the control terminals of the memory cells according to preset programming data by using the word line driver, reads data from the memory cells by using the bit line circuit, and determines whether the data of each memory cell is normal according to the data read from the memory cells. When the data of specific memory cells is not normal, the controller performs a second programming process to the specific memory cells.

Abstract: A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result.

Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Abstract: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

Abstract: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

Abstract: A flash memory and a regulated voltage generator thereof. The regulated voltage generator includes a charge pump having an output terminal outputting a first voltage, a control circuit coupled to the output terminal of the charge pump and having first and second output terminals outputting a second voltage and a charge pump control signal, respectively, and a Field Effect Transistor (FET) in diode mode. The FET is coupled between the output terminal of the charge pump and the first output terminal of the control circuit. The charge pump adjusts the first voltage according to the charge pump control signal.

Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Abstract: A voltage adjusting circuit is provided. The voltage adjusting circuit for adjusting the output voltages supplied by voltage sources includes a test control device, a multiplexer, a comparator, and a built in self test (BIST) device. The test control device selects one of the voltage sources as a testing voltage source, and outputs a selecting command for selecting the testing voltage source and a target voltage corresponding to the testing voltage source. The multiplexer is coupled to the voltage sources, receives an enablement signal, and outputs a voltage supplied by the testing voltage source as a testing voltage according to the enablement signal. The comparator compares the voltage levels of the testing voltage and the target voltage, and outputs a comparison result.

Abstract: A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

Abstract: An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.