Patents by Inventor Chun-Yi Yang
Chun-Yi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978664Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.Type: GrantFiled: July 29, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240113166Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.Type: ApplicationFiled: February 15, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu, Ya-Yi Tsai, Shu-Yuan Ku, Shun-Hui Yang
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Publication number: 20230280391Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung CHEN, Chun-Yi YANG, Chan-Hong CHERN
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Patent number: 11680978Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: GrantFiled: September 30, 2020Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ann Lai, Ruo-Rung Huang, Kun-Lung Chen, Chun-Yi Yang, Chan-Hong Chern
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Publication number: 20230005852Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11444046Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: GrantFiled: August 27, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 11341014Abstract: An information handling system includes an embedded controller that subsequent to a determination that a power button is activated, may determine a sequence of unplugging a connector from a port within a time threshold and subsequently plugging the connector from the port within another time threshold. The embedded controller may determine a hotkey associated with the sequence of unplugging the connector from the port and subsequently plugging the connector to the port, and execute a function based on the hotkey.Type: GrantFiled: October 2, 2020Date of Patent: May 24, 2022Assignee: Dell Products L.P.Inventors: Craig L. Chaiken, Chun Yi Yang
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Publication number: 20220107873Abstract: An information handling system includes an embedded controller that subsequent to a determination that a power button is activated, may determine a sequence of unplugging a connector from a port within a time threshold and subsequently plugging the connector from the port within another time threshold. The embedded controller may determine a hotkey associated with the sequence of unplugging the connector from the port and subsequently plugging the connector to the port, and execute a function based on the hotkey.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Craig L. Chaiken, Chun Yi Yang
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Publication number: 20220099726Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Yu-Ann LAI, Ruo-Rung HUANG, Kun-Lung CHEN, Chun-Yi YANG, Chan-Hong CHERN
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Patent number: 11163886Abstract: An information handling system embedded controller does not initiate a chipset having secure execution of chipset firmware unless the chipset firmware validates against error correcting checksums inserted into the embedded controller firmware. Comparing checksums calculated from chipset firmware against expected checksum values for the chipset firmware prevents secure chipset initiation failure due to bit errors associated with chipset firmware storage in flash memory.Type: GrantFiled: September 28, 2018Date of Patent: November 2, 2021Assignee: Dell Products L.P.Inventors: Craig Lawrence Chaiken, Chun Yi Yang
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Patent number: 11011462Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.Type: GrantFiled: November 14, 2016Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Chun-Yi Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang
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Publication number: 20200395320Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Patent number: 10840371Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: GrantFiled: October 25, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
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Patent number: 10804231Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.Type: GrantFiled: May 22, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hong Chang, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
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Publication number: 20200104504Abstract: An information handling system embedded controller does not initiate a chipset having secure execution of chipset firmware unless the chipset firmware validates against error correcting checksums inserted into the embedded controller firmware. Comparing checksums calculated from chipset firmware against expected checksum values for the chipset firmware prevents secure chipset initiation failure due to bit errors associated with chipset firmware storage in flash memory.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Dell Products L.P.Inventors: Craig Lawrence Chaiken, Chun Yi Yang
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Publication number: 20200066902Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: ApplicationFiled: October 25, 2019Publication date: February 27, 2020Inventors: Tsai-Feng YANG, Chih-Heng SHEN, Chun-Yi YANG, Kun-Ming HUANG, Po-Tao CHU, Shen-Ping WANG
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Patent number: 10558779Abstract: A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.Type: GrantFiled: May 31, 2018Date of Patent: February 11, 2020Assignee: AnaGlobe Technology, Inc.Inventors: Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang, Chih-Che Lin, Chun-Yi Yang
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Publication number: 20190370433Abstract: A method of redistribution layer routing for 2.5D integrated circuit packages is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a MMSIM (modulus-based matrix splitting iteration method) based routing to assign pre-assignment nets to tracks such that total vertical distance from each bump pair to the assigned track is minimized; and performing a MWMCBM (minimum weighted maximum cardinality bipartite matching) based routing for bumps connected to the assigned tracks according to matching result to complete redistribution layer routing for integrated circuit packages.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Inventors: Chun-Han CHIANG, Fu-Yu CHUANG, Yao-Wen CHANG, Chih-Che LIN, Chun-Yi YANG
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Patent number: 10461183Abstract: A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang