Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.

Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

Abstract: Systems, methods, and non-transitory computer-readable media are provided for detecting and monitoring fraudulent entity networks in a networked environment. The networked environment can be mapped with cross account clustering to identify nodes associated with one or more entity networks in the networked environment and can identify whether the one or more entity networks are fraudulent entity networks based on a determination that one or more nodes in the one or more entity networks is a source of malignant content. Upon detecting the fraudulent entity networks, embodiments of the present disclosure can alert parties that may be affected by the one or more fraudulent entity networks and/or can initiate one or more actions against the fraudulent entity network.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A memory device is provided, including a first word line driver configured to activate a first word line. The first word line driver includes a first transistor configured to operate in response to a first control signal having a first voltage level to transmit a first word line voltage to a first word line and a second transistor coupled between the first word line and a supply voltage terminal and configured to be turned off in response to a second control signal having a second voltage level different from the first voltage level.

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.