Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: A memory device is provided, including a first word line driver configured to activate a first word line. The first word line driver includes a first transistor configured to operate in response to a first control signal having a first voltage level to transmit a first word line voltage to a first word line and a second transistor coupled between the first word line and a supply voltage terminal and configured to be turned off in response to a second control signal having a second voltage level different from the first voltage level.

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

Abstract: A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

Abstract: The manufacturing method of titanium dioxide solution includes: mixing choline chloride, urea, boric acid, and titanium tetrachloride to form a first solution, wherein a molar concentration ratio of choline chloride to urea is 1:2, a molar concentration of titanium tetrachloride is 0.2 M to 0.4 M, and weight/volume of boric acid is 5 g/300 ml to 15 g/300 ml; and heating the first solute ion to form a second solution, wherein the second solution contains carbon/nitrogen doped titanium dioxide. In the manufacturing method of the present disclosure, the deep eutectic solution formed by choline chloride and urea may be used as a solvent, and may also be used as a carbon source and/or a nitrogen source. Therefore, titanium dioxide may be doped with carbon and/or nitrogen during the formation process.

Abstract: A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: The present disclosure provides a manufacturing method of a titanium dioxide solution and a titanium dioxide film. The manufacturing method of the titanium dioxide solution includes: mixing choline chloride, urea, boric acid, and titanium tetrachloride to form a first solution, wherein a molar concentration ratio of choline chloride to urea is 1:2, a molar concentration of titanium tetrachloride is 0.2 M to 0.4 M, and weight/volume of boric acid is 5 g/300 ml to 15 g/300 ml; and heating the first solution to form a second solution, wherein the second solution contains carbon/nitrogen doped titanium dioxide. In the manufacturing method of the present disclosure, the deep eutectic solution formed by choline chloride and urea may be used as a solvent, and may also be used as a carbon source and/or a nitrogen source. Therefore, titanium dioxide may be doped with carbon and/or nitrogen during the formation process.

Abstract: The present disclosure provides a manufacturing method of indium tin oxide, including: providing a first electrolyte including choline chloride, urea, indium chloride, boric acid, and ascorbic acid; disposing a workpiece, wherein at least a part of the workpiece is in contact with the first electrolyte; heating the first electrolyte to 60° C.-95° C.; applying a first operating current to electroplate indium onto the workpiece; providing an second electrolyte including choline chloride, urea, tin chloride, boric acid, and ascorbic acid; disposing the indium-coated workpiece, wherein at least a part of the workpiece is in contact with the second electroplate; heating the second electroplate to 60° C.-95° C.; applying a second operating current to electroplate tin onto the workpiece; and annealing the indium and tin on the workpiece to form indium tin oxide in an oxygen environment.

Abstract: The present disclosure provides a manufacturing method of aluminum nitride, including: providing an electrolyte including choline chloride, urea, aluminum chloride, boric acid, and ascorbic acid; disposing a workpiece, wherein at least a part of the workpiece is in contact with the electroplating solution; heating the electrolyte to within 60° C.-95° C.; applying an operating current to electroplate aluminum onto the workpiece; and annealing the aluminum on the workpiece to form aluminum nitride.

Abstract: The present disclosure provides a manufacturing method of indium tin oxide, including: providing a first electrolyte including choline chloride, urea, indium chloride, boric acid, and ascorbic acid; disposing a workpiece, wherein at least a part of the workpiece is in contact with the first electrolyte; heating the first electrolyte to 60° C.-95° C.; applying a first operating current to electroplate indium onto the workpiece; providing an second electrolyte including choline chloride, urea, tin chloride, boric acid, and ascorbic acid; disposing the indium-coated workpiece, wherein at least a part of the workpiece is in contact with the second electroplate; heating the second electroplate to 60° C.-95° C.; applying a second operating current to electroplate tin onto the workpiece; and annealing the indium and tin on the workpiece to form indium tin oxide in an oxygen environment.

Abstract: A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.

Abstract: The present invention is a method of metal polishing and oxidation film process applied on a metal workpiece. The process comprises (a) providing the metallic workpiece in an electrolysis polishing liquid; (b) a temperature control device controlling a liquid temperature of the electrolysis polishing liquid; (c) a voltage supply device to exercising an operating voltage between the metallic workpiece and the electrolysis polishing liquid; (d) polishing the surface of the metallic workpiece and forming an oxidation layer by regulating the temperature control device and the voltage supply device; and (e) determining a film thickness of the oxidation layer formed on the metallic workpiece according to an operation time, wherein the film thickness is related to a roughness and a color displayed on the metallic workpiece. The metallic workpiece may be dyed together during the polishing process without adding any dyes. The present invention further provides a system of alloy oxidation film process.