Patents by Inventor Chun-You Wang

Chun-You Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240106197
    Abstract: A laser automatic compensation control device includes a controller, a digital array, a decoder, a compensation array and a synchronizer. The controller is configured for receiving a number of laser energy signals and comparing each laser energy signal with a corresponding preset energy value to obtain a corresponding output digital signal. The digital array is electrically connected to the controller and configured for storing the output digital signals. The decoder is electrically connected to the digital array and configured for converting the output digital signals into a number of analog compensation signals. The compensation array is electrically connected to the decoder and configured for storing the analog compensation signals. The synchronizer is electrically connected to the compensation array and configured for receiving the analog compensation signals, and synchronously outputting the analog compensation signals to a laser diode array.
    Type: Application
    Filed: November 1, 2022
    Publication date: March 28, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jia-You WANG, Fu-Shun HO, Chun-Chieh YANG, Chih-Chun CHEN
  • Patent number: 7526703
    Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: April 28, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Min-Shu Wang, Chun-You Wang, Chun-Chih Yang
  • Publication number: 20070101226
    Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.
    Type: Application
    Filed: July 11, 2006
    Publication date: May 3, 2007
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Min-Shu Wang, Chun-You Wang, Chun-Chih Yang
  • Patent number: D916262
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 13, 2021
    Inventors: Mu-Mian Wang, Chun-You Wang, Yong Hou
  • Patent number: D919064
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: May 11, 2021
    Inventors: Mu-Mian Wang, Chun-You Wang, Yong Hou