Abstract: A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units.

Abstract: An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.

Abstract: A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit cell made up of six transistors. The word line decoder is used for decoding a word line of the SRAM bit cell array such that the word line is activated at a starting time and is deactivated at a ending time. The reference bit line device is connected between the SRAM array and the word line decoder and is used for pre-deactivating the word line at a predetermined time before the ending time such that a voltage difference between a bit line and a bit line bar of the SRAM bit cell is equal to a predetermined voltage.

Abstract: An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.

Abstract: A static random access memory (SRAM) is provided. The SRAM structure includes an SRAM array, a word line decoder, and a reference bit line device. The SRAM array comprises at least one SRAM bit cell made up of six transistors. The word line decoder is used for decoding a word line of the SRAM bit cell array such that the word line is activated at a starting time and is deactivated at a ending time. The reference bit line device is connected between the SRAM array and the word line decoder and is used for pre-deactivating the word line at a predetermined time before the ending time such that a voltage difference between a bit line and a bit line bar of the SRAM bit cell is equal to a predetermined voltage.

Abstract: A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state.

Abstract: A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.

Abstract: A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Abstract: A method for controlling a memory device includes: categorizing a plurality of sub-memory units of the memory device into a first group of sub-memory units and a second group of sub-memory units; sequentially storing pixel data of a plurality of pixels being displayed on a first line of a display screen into the sub-memory units of the first group of sub-memory units; sequentially storing the pixel data of a plurality of pixels being displayed on a second line next to the first line of the display screen into the sub-memory units of the second group of sub-memory units; and, starting from a next but one sub-memory unit to the first selected sub-memory unit, sequentially storing the pixel data of a plurality of pixels being displayed on a third line next to the second line of the display screen into the sub-memory units of the first group of sub-memory units.

Abstract: A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.

Abstract: A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state.

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract: A pad driving circuit includes an output control circuit, a voltage pump circuit, a first buffer series, and a second buffer series. The output control circuit controls whether a pad circuit can pass an input signal, in which the output control circuit enables the pad circuit to output the input signal when an enable signal is asserted. The voltage pump circuit generates a negative supply voltage having voltage less than a zero volt. The first buffer series, electrically connected between the output control circuit and the pad circuit, drives the pad circuit with a positive supply voltage and the negative supply voltage from the voltage pump circuit. The second buffer series drives the pad circuit with a ground voltage and the positive supply voltage.

Abstract: A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.