Patents by Inventor Chun-Yu CHUANG

Chun-Yu CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11719643
    Abstract: A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 8, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chun-Yu Chuang, Pin-Hsuan Yeh, Chao-Ming Tsen, Ching-Wei Yu, Wei-Chung Chao, Yung-Hsiang Wang, Cheng-Chien Li
  • Publication number: 20190360938
    Abstract: A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: CHUN-YU CHUANG, PIN-HSUAN YEH, CHAO-MING TSEN, CHING-WEI YU, WEI-CHUNG CHAO, YUNG-HSIANG WANG, CHENG-CHIEN LI
  • Patent number: 10237091
    Abstract: According to one exemplary embodiment, a parallel scheduling method for network data transmission is provided. This method generates a corresponding modulus condition set for each weight in a weight set, with each modulus condition of the modulus condition set having a modulus operation, and a divisor and a remainder for the modulus operation, uses a network node to transmit the modulus condition set corresponding to said each weight to a transmitting node corresponding to the weigh. Based on the modulus condition set, the transmitting node transmits a plurality of data chunks, and at least one receiving node receives the plurality of data chunks, wherein each data chunk corresponding to a sequence number, and the sequence number matches a corresponding modulus condition in the modulus condition set.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 19, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Hsin Chang, Kun-Hsien Lu, Chun-Yu Chuang, Shih-Yu Liu
  • Publication number: 20160225882
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 4, 2016
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai
  • Patent number: 9406784
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: August 2, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai
  • Publication number: 20150326633
    Abstract: According to one exemplary embodiment, a parallel scheduling method for network data transmission is provided. This method generates a corresponding modulus condition set for each weight in a weight set, with each modulus condition of the modulus condition set having a modulus operation, and a divisor and a remainder for the modulus operation, uses a network node to transmit the modulus condition set corresponding to said each weight to a transmitting node corresponding to the weigh. Based on the modulus condition set, the transmitting node transmits a plurality of data chunks, and at least one receiving node receives the plurality of data chunks, wherein each data chunk corresponding to a sequence number, and the sequence number matches a corresponding modulus condition in the modulus condition set.
    Type: Application
    Filed: December 22, 2014
    Publication date: November 12, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Hsin CHANG, Kun-Hsien LU, Chun-Yu CHUANG, Shih-Yu LIU