Patents by Inventor Chun-Yu CHUANG

Chun-Yu CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142428
    Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Yu TSAI, Hung-Sheng LIN, Cheng-Da KO, Chun-Te CHUANG
  • Publication number: 20240136299
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20240113143
    Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 4, 2024
    Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11719643
    Abstract: A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 8, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chun-Yu Chuang, Pin-Hsuan Yeh, Chao-Ming Tsen, Ching-Wei Yu, Wei-Chung Chao, Yung-Hsiang Wang, Cheng-Chien Li
  • Publication number: 20190360938
    Abstract: A method for detecting dust mite antigens includes the steps of collecting a dust sample, applying an extraction and cleanup procedure for dust mite antigens from the dust sample in order to obtain a sample solution ready for measurement, and placing the sample solution on a SERS chip without immunological modification and under a Raman spectrometer for SERS detection in order to identify whether any dust mite antigens exist in the sample solution.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 28, 2019
    Inventors: CHUN-YU CHUANG, PIN-HSUAN YEH, CHAO-MING TSEN, CHING-WEI YU, WEI-CHUNG CHAO, YUNG-HSIANG WANG, CHENG-CHIEN LI
  • Patent number: 10237091
    Abstract: According to one exemplary embodiment, a parallel scheduling method for network data transmission is provided. This method generates a corresponding modulus condition set for each weight in a weight set, with each modulus condition of the modulus condition set having a modulus operation, and a divisor and a remainder for the modulus operation, uses a network node to transmit the modulus condition set corresponding to said each weight to a transmitting node corresponding to the weigh. Based on the modulus condition set, the transmitting node transmits a plurality of data chunks, and at least one receiving node receives the plurality of data chunks, wherein each data chunk corresponding to a sequence number, and the sequence number matches a corresponding modulus condition in the modulus condition set.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 19, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Hsin Chang, Kun-Hsien Lu, Chun-Yu Chuang, Shih-Yu Liu
  • Publication number: 20160225882
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 4, 2016
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai
  • Patent number: 9406784
    Abstract: A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: August 2, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Chun-Yu Chuang, Yi-Lin Hsu, Liang-Chuan Lai
  • Publication number: 20150326633
    Abstract: According to one exemplary embodiment, a parallel scheduling method for network data transmission is provided. This method generates a corresponding modulus condition set for each weight in a weight set, with each modulus condition of the modulus condition set having a modulus operation, and a divisor and a remainder for the modulus operation, uses a network node to transmit the modulus condition set corresponding to said each weight to a transmitting node corresponding to the weigh. Based on the modulus condition set, the transmitting node transmits a plurality of data chunks, and at least one receiving node receives the plurality of data chunks, wherein each data chunk corresponding to a sequence number, and the sequence number matches a corresponding modulus condition in the modulus condition set.
    Type: Application
    Filed: December 22, 2014
    Publication date: November 12, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Hsin CHANG, Kun-Hsien LU, Chun-Yu CHUANG, Shih-Yu LIU