Abstract: Disclosed herein are related to devices and methods for communication. In one aspect, a device includes a first processor and a second processor. The first processor may be configured to generate a first set of packets associated with an application data unit in a first layer corresponding to content data. Each packet of the first set of packets may include a flag indicative of an association with the application data unit. The second processor may be configured to generate a second set of one or more packets in a second layer for transmission, in response to determining that the first set of packets is associated with the application data unit according to flags of the first set of packets. The second processor may be configured to schedule to transmit the second set of one or more packets in the second layer within a defined time period.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module, arranged to read data in a memory cell; and a control module, electrically connected to the amplification module. In a first offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first inverter and a second inverter, and each of the first inverter and the second inverter is an inverter an input terminal and an output terminal connected to each other; and in a second offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a current mirror structure.

Abstract: The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

Abstract: The disclosure provides a Sense Amplifier (SA), a memory and a method for controlling the SA, and relates to the technical field of semiconductor memories. The SA includes: an amplifier module; an offset voltage storage unit electrically connected to the amplifier module and configured to store an offset voltage of the amplifier module in an offset elimination stage of the SA; and a load compensation unit electrically connected to the amplifier module and configured to compensate a difference between loads of the amplifier module in an amplification stage of the SA. The disclosure may improve an accuracy of reading data of the SA.

Abstract: In one embodiment, the present invention is a system for organizing data flow for two dimensional digital image processing. The system includes a memory access module for accessing an external memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Abstract: In one embodiment, the present invention is a system for organizing data flow for two dimensional digital image processing. The system includes a memory access module for accessing an external memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Abstract: In one embodiment, the present invention is a system for two dimensional digital image processing. The system includes a memory access module for accessing a memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Abstract: In one embodiment, the present invention is a system for two dimensional digital image processing. The system includes a memory access module for accessing a memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.

Abstract: In one embodiment, the present invention is a system for two dimensional digital image processing. The system includes a memory access module for accessing a memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data neede for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.