Patents by Inventor Chun-Yu Shei

Chun-Yu Shei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10949182
    Abstract: Systems and methods generate code from a source program where the generated code may be compiled and executed on a Graphics Processing Unit (GPU). A parallel loop analysis check may be performed on regions of the source program identified for parallelization. One or more optimizations also may be applied to the source program that convert mathematical operations into a parallel form. The source program may be partitioned into segments for execution on a host and a device. Kernels may be created for the segments to be executed on the device. The size of the kernels may be determined, and memory transfers between the host and device may be optimized.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 16, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Girish Venkataramani, Rama P. Kokku, Jayaprabha Shankar, James L. Brock, Chun-Yu Shei, Vijaya Raghavan
  • Patent number: 10157045
    Abstract: Systems and methods may automatically generate code for deep learning networks. The systems methods may provide a code generation framework for generating target specific code. The code generation framework may include one or more predefined class hierarchies for constructing objects of the generated code. The objects of the class hierarchies may provide an interface to predefined libraries of deep learning functions optimized for use on a target platform. The systems and methods may perform one or more optimizations on the code being generated.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 18, 2018
    Assignee: The MathWorks, Inc.
    Inventors: Girish Venkataramani, Rama P. Kokku, Jayaprabha Shankar, James L. Brock, Chun-Yu Shei, Vijaya Raghavan, Yaohung Tsai
  • Publication number: 20180157471
    Abstract: Systems and methods generate code from a source program where the generated code may be compiled and executed on a Graphics Processing Unit (GPU). A parallel loop analysis check may be performed on regions of the source program identified for parallelization. One or more optimizations also may be applied to the source program that convert mathematical operations into a parallel form. The source program may be partitioned into segments for execution on a host and a device. Kernels may be created for the segments to be executed on the device. The size of the kernels may be determined, and memory transfers between the host and device may be optimized.
    Type: Application
    Filed: November 17, 2017
    Publication date: June 7, 2018
    Inventors: Girish Venkataramani, Rama P. Kokku, Jayaprabha Shankar, James L. Brock, Chun-Yu Shei, Vijaya Raghavan
  • Publication number: 20180136912
    Abstract: Systems and methods may automatically generate code for deep learning networks. The systems methods may provide a code generation framework for generating target specific code. The code generation framework may include one or more predefined class hierarchies for constructing objects of the generated code. The objects of the class hierarchies may provide an interface to predefined libraries of deep learning functions optimized for use on a target platform. The systems and methods may perform one or more optimizations on the code being generated.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 17, 2018
    Inventors: Girish Venkataramani, Rama P. Kokku, Jayaprabha Shankar, James L. Brock, Chun-Yu Shei, Vijaya Raghavan, Yaohung Tsai
  • Patent number: 9740529
    Abstract: A system and method for optimizing a system design that includes two or more components, where at least one component is to be implemented using a constrained resource. From an initial schedule, the resource having a longest span time between a start busy time slot and an end busy time slot is identified. The schedule for the other resources is then also extended to the span time. The resulting design can be made synchronous by inserting up-sampler and down-sampler function blocks before and after any strongly connected components.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 22, 2017
    Assignee: The MathWorks, Inc.
    Inventors: Chun-Yu Shei, Girish Venkataramani