Abstract: A bone substitute composition includes a bone substitute matrix and a conditioning solution. The bone substitute matrix includes 85% to 98% by weight of alkaline calcium phosphate powder, 1% to 10% by weight of a polymer, and 1% to 5% by weight of a crosslinker. The conditioning solution includes 90% to 97% by weight of water, 1% to 5% by weight of a phosphate, and 1% to 5% by weight of a water-soluble acidic compound.

Abstract: A measurement assistance system and method are provided. The measurement assistance system includes: a measurement platform, having an operation area configured for a to-be-measured object and a measurement tool to be placed; a camera, arranged on the measurement platform and configured to obtain a measurement image; and a server module, electrically connected to the camera and configured to execute a measurement tool identification program, a measurement part identification program, and a measurement posture identification program according to the measurement image, and determine whether a measurement tool appearance image, a measurement part image, and a measurement posture image are correct. The server module has a processing unit. When the measurement tool appearance image, the measurement part image, and the measurement posture image are all correct, a measurement result is generated according to measurement data.

Abstract: An air sterilization device for plumbing air ventilation piping and a system therefor with sensors, network connectivity, monitoring and controlling. The air sterilization device is disposed coaxially with a plumbing ventilating pipe to ensure air escaping out from the ventilating pipe has been sterilized.

Abstract: An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.

Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.

Abstract: A mixer with a filtering function and a method for linearization of the mixer are provided. The mixer includes at least one amplifier, a transconductance device and a feedback network. The at least one amplifier is configured to output a filtered voltage signal according to an input voltage signal. The transconductance device is coupled to the at least one amplifier, and is configured to generate a filtered current signal according to the filtered voltage signal. The feedback network is coupled between any output terminal among at least one output terminal of the transconductance device and an input terminal of the at least one amplifier. More particularly, the mixer is configured to output a modulated signal according to the filtered current signal.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Abstract: A head-mounted display includes a display device, a connecting structure and a head abutting portion. The connecting structure is in a shape of strip. The connecting structure has two opposite ends. The ends are respectively connected with the display device. The connecting structure and the display device define an accommodation space. The accommodation space is configured to accommodate a head of a user. The head abutting portion is pivotally connected with the connecting structure. The head abutting portion is at least partially located between the connecting structure and the display device. The head abutting portion is configured to abut against the head of the user.

Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Abstract: A gas sensing device for detecting a to-be-detected substance in a respiratory gas exhaled by a user includes a housing permitting entrance of the respiratory gas, and a sensing module disposed in the housing. The sensing module includes a light chamber permitting the respiratory gas to pass therethrough, a light source unit emitting light into the light chamber, first and second light sensing units outputting respectively first and second detected signals indicating first and second detected intensities respectively of first and second portions of the light whose wavelengths fall within first and second wavelength ranges, respectively, and a processing unit electrically connected to the first and second light sensing units and determining, based on the first and second detected signals, that the to-be-detected substance exists in the respiratory gas when a difference occurs in each of the first and second detected intensities over time.

Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.

Abstract: Defect detection method for a semi-conducting bedding layer of a power cable includes: obtaining a length parameter, a corrugation pitch parameter, radius parameters, and a thickness parameter of a power cable; obtaining a first resistance value between a shield and a corrugated sheath, and calculating a second resistance value of the shield based on the length parameter and the corrugation pitch parameter; calculating a radial resistance value of the semi-conducting bedding layer based on the first resistance value and the second resistance value; determining a contact angle of a critical point of contact between the corrugated sheath and the semi-conducting bedding layer based on the radius parameters and the thickness parameter; calculating volume resistivity of the semi-conducting bedding layer based on the radial resistance value and the contact angle; and comparing the volume resistivity with a preset evaluation parameter to obtain a defect detection result of the semi-conducting bedding layer.

Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: An auto-configuration method for a time-sensitive networking (TSN) system includes obtaining, by a first OPC UA client module, a TSN configuration of a stream; transmitting, by the first OPC UA client module, the TSN configuration to an OPC UA server module of a centralized user configuration (CUC) in the TSN system; obtaining, by the CUC, a routing information and scheduling of the stream according to the TSN configuration and a network topology; sending, by the first OPC UA client module, a request to the OPC UA server to obtain the routing information and scheduling of the stream; and configuring the routing information and scheduling of the stream to a plurality of end stations in the TSN system after the plurality of end stations are online.

Abstract: A core wire includes: an inner conductor; and an insulating layer covering the inner conductor, wherein the insulation layer is made by 3D printing process, the insulating layer includes a first semi-insulating layer and a second semi-insulating layer, each of the first semi-insulating layer and the second semi-insulating layer has a groove that matchingly accommodates the shape of the inner conductor, and the first semi-insulating layer and the second semi-insulating layer are combined together.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.