Abstract: A node unit includes a base plate, at least one function module, and a non-conductive coolant. The function module includes a heat-generating element, a heat-dissipating structure, and a pump. The heat-generating element is disposed on the base plate, the heat-dissipating structure is disposed on the heat-generating element, and the pump is disposed on the heat-dissipating structure. The base plate and the at least one function module are immersed in the non-conductive coolant. The pump is configured to drive the non-conductive coolant to flow into the heat-dissipating structure and discharge from the heat-dissipating structure. An electronic device and an immersion cooling type equipment are also mentioned.

Abstract: Resistors and method of forming the same are provided. A device structure according to the present disclosure includes a substrate, a first intermetal dielectric (IMD) layer over the substrate, a resistor that includes a first resistor layer over the first IMD layer, a second resistor layer over the first resistor layer, and a third resistor layer over the second resistor layer, a second IMD layer over the first IMD layer and the resistor, a first contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer, and a second contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source/drain region and extending vertically along a sidewall of the silicide. A source/drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.

Abstract: A touch control circuit for use in a display device includes: a plurality of analog-to-digital converters and a controller. Each of the analog-to-digital converters is coupled to at least one of a plurality of touch sensing electrodes and at least one of a plurality of source drivers of the display device. At least one of the analog-to-digital converters is configured to generate a first measured digital code according to an output voltage outputted by at the least one of the source drivers. The controller is coupled to the analog-to-digital converters, and configured to compare the first measured digital code with an input digital code that the output voltage of the at the least one of the source drivers corresponds to, thereby to generate a first safety detection result regarding the at least one of the source drivers.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. A bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: A knob on a touch panel includes a rotary wheel, a common pad, at least one sensing pad, a plurality of connectors and a conductive ring. The rotary wheel is mounted on the touch panel. The common pad is deployed on the touch panel. The at least one sensing pad is deployed on the touch panel. Each of the plurality of connectors is coupled between the rotary wheel and one pad among the at least one sensing pad and the common pad, to control each of the at least one sensing pad to be coupled to the common pad or not through the rotary wheel according to an operation of the knob. The conductive ring is deployed on a surface of the rotary wheel, to detect a touch object.

Abstract: A damper device and an electronic apparatus are provided. The damper device includes a first holder, a first damper component and a first gel. The first damper component includes a first protrusion part and a first bar part. The first protrusion part includes a first surface. The first bar part includes a first free end and a first fixed end. The first protrusion part is fixed on the first free end, the first fixed end is fixed on the first holder and the first surface protrudes outward from the first free end. The first free end and the first protrusion part are inserted into the first gel, and the first gel moves along the radial direction of the first bar part relative to the first bar part.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: Provided is a bioreactor apparatus including: a liquid storage chamber for storing a liquid containing a first ion; a pump; a culture chamber for accommodating the liquid and cells to be cultured; and an ion-exchange chamber accommodating an ion-exchange substrate containing a second ion. Affinity of the second ion to the ion-exchange substrate is lower than affinity of the first ion to the ion-exchange substrate, or molar concentration of the second ion far outweigh molar concentration of the first ion. The storage chamber, the pump, the culture chamber and the ion-exchange chamber are connected via pipelines to form a closed loop, and the pump is configured to provide pressure to drive flow of the liquid in the closed loop. Also provided are a method for regulating ion concentration by the ion-exchange substrate and a method for cell culture by the bioreactor apparatus.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.