Patents by Inventor Chun-Yuan Chen

Chun-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278273
    Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12272634
    Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20250113565
    Abstract: Embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. The buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.
    Type: Application
    Filed: February 2, 2024
    Publication date: April 3, 2025
    Inventors: Lo-Heng CHANG, Huan-Chieh SU, Chun-Yuan CHEN, Sheng-Tsung WANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12266700
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Grant
    Filed: May 6, 2024
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Shih-Chuan Chiu, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12266658
    Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12266566
    Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin
  • Patent number: 12261196
    Abstract: In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lu-Sheng Chou, Hsuan-Han Tseng, Chun-Yuan Chen, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20250087578
    Abstract: A semiconductor device and a method of manufacturing thereof are provided. The method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Sheng-Tsung Wang, Huan-Chieh Su, Chih-Hao Wang, Meng-Huan Jao
  • Patent number: 12243823
    Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12243907
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Publication number: 20250072049
    Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Chien WU, Chun-Yuan CHEN, Huan-Chieh SU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12230572
    Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin, Wei-An Lai, Ming Chian Tsai, Jiann-Tyng Tzeng, Hou-Yu Chen, Chun-Yuan Chen, Huan-Chieh Su
  • Patent number: 12224212
    Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20250046718
    Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.
    Type: Application
    Filed: November 30, 2023
    Publication date: February 6, 2025
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250048710
    Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 6, 2025
    Inventors: Lo-Heng CHANG, Huan-Chieh SU, Chun-Yuan CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20250029925
    Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.
    Type: Application
    Filed: July 29, 2024
    Publication date: January 23, 2025
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20250024633
    Abstract: A heat dissipation module includes a housing defining a receiving space for accommodating a fan, a turntable, and an expansion mechanism. The housing includes a top plate and two side walls connected to opposite ends of the top plate. The fan is configured for generating airflow from one side wall to the other. The turntable is connected to the expansion mechanism. The turntable rotates into a locked position to extend the expansion mechanism to protrude from the housing, and the turntable deviates from the locked position to retract the expansion mechanism back into the housing. An electronic device including the heat dissipation module is also provided.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 16, 2025
    Inventor: CHUN-YUAN CHEN
  • Publication number: 20250006807
    Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240429292
    Abstract: The present disclosure describes a semiconductor device having a contact structure isolated from a source/drain structure. The semiconductor structure includes a gate structure on a substrate, first and second source/drain (S/D) structures on opposite sides of the gate structure, an isolation layer on the second S/D structure, a third S/D structure adjacent to and separate from the second S/D structure, and a S/D contact structure on the isolation layer and the third S/D structure. The isolation layer separates the S/D contact structure from the second S/D structure.
    Type: Application
    Filed: October 18, 2023
    Publication date: December 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Kuo-Cheng CHIANG, Chih-Hao WANG