Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

Abstract: A physical layer module and a network module are provided. The network module includes the physical layer module and a media access control module. The physical layer module includes a group decoder, an input selection module, and a device module. The group decoder decodes a common input data signal generated according to a management data input/output signal to generate a group selection signal. The input selection module includes X input circuits being classified into M groups. The X input circuits generate X device input data according to the common input data signal and the group selection signal. The device module includes K physical layer devices classified into M groups. The K physical devices receive X device input data from the X input circuits. An m-th group corresponds to at least one input circuit and N[m] physical layer devices.

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.

Abstract: A method for managing a secure library supporting data storage and an associated electronic device are provided. The method includes: configuring at least one first sub-region and at least one second sub-region in a secure library region within a non-volatile memory to be an instruction region and a data region of the secure library, respectively; after the secure library is enabled, utilizing a memory controller to prevent any write operation and any erase operation from being applied to the secure library region, in order to protect the predetermined instructions and the predetermined data respectively positioned in the instruction region and the data region; and after the secure library is enabled, utilizing at least one processor to read the instruction region and the data region via an instruction port and a data port of the at least one processor, respectively.

Abstract: A circuit system includes a first power source, a second power source, a first interface circuit, a second interface circuit and an isolation circuit. The first interface circuit is included in a first power domain. The second interface circuit is includes in a second power domain. The bus signal group from the first interface circuit is transmitted to the second interface circuit through the isolation circuit. In a power-saving mode, the bus signal group in a floating state can be effectively isolated by the isolation circuit. If a sudden power interruption event occurs when the circuit system is in the normal working mode, the bus signal group in the floating state is isolated by the isolation circuit. Moreover, the isolation circuit is capable of filtering off the incomplete transaction data, and thus the second interface circuit is not suffered from malfunction.

Abstract: A method of executing an initial program load in an electronic device is provided. The electronic device includes a chip. The chip is connected with a storage device. The method includes the following steps. First, checking data and a characteristic value are read from the storage device. Then, an algorithm parameter is acquired from the checking data. Then, the checking data and the characteristic value are verified according to a specified checking algorithm and the algorithm parameter. If a result of the specified checking algorithm passes, a boot code is executed. If the result of the specified checking algorithm fails, a notification signal is issued.

Abstract: An interrupt management system and a management method thereof are provided. The interrupt management system includes a processor and an interrupt signal expanding controller. The processor receives a plurality of original interrupt signals. The interrupt signal expanding controller includes a decoder and an interrupt vector table. The decoder receives a plurality of expanding interrupt request signals, and decodes the expanding interrupt request signals to generate the original interrupt signals, where number of the expanding interrupt request signals is larger than number of the original interrupt signals. The interrupt vector table stores a plurality of interrupt vectors. The decoder reads one of the interrupt vectors to obtain an accessed interrupt vector according to the expanding interrupt request signals, and the interrupt signal expanding controller transmits the accessed interrupt vector to the processor.

Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided.

Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided.

Abstract: An apparatus and a method for video frame rotation are provided. The apparatus includes a synchronous dynamic random access memory (SDRAM) and a video rotation circuit. The video rotation circuit is coupled to the SDRAM. The video rotation circuit sequentially writes a plurality of pixels of a video frame into the SDRAM in a row-by-row scanning manner. The video rotation circuit divides a plurality of columns of the video frame into a plurality of column sets, so as to divide each of the rows of the video frame into a plurality of sub-rows. The video rotation circuit performs an internal column-set scanning for each of the column sets in a column-set-by-column-set manner, so as to discretely read the sub-rows from the SDRAM.

Abstract: A controller coupled to a plurality of hardware modules is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.

Abstract: A signal transceiving apparatus with a power provider, which comprises: a power receiving interface, for receiving a first power; a power output interface, for outputting a second power; a signal transferring apparatus, for receiving a third power, receiving input data and for transferring the input data to an output data matching a target electronic apparatus spec; and a signal output interface, for outputting the output data to the target electronic apparatus; wherein the signal transforming apparatus does not provide power to the target electronic apparatus, where the second power, the third power are generated according to the first power.