Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Abstract: A method of logical channel prioritization and a device thereof are provided.

Abstract: A method and a user equipment for reporting a remaining delay budget information are provided. The method includes: receiving a radio resource control configuration, wherein the radio resource control configuration indicates the user equipment to report the remaining delay budget information of a logical channel or a logical channel group through a status report message; determining whether a triggering condition is met, wherein the triggering condition is associated with a threshold of remaining delay budget; and in response to the triggering condition being met, transmitting the status report message including the remaining delay budget information, wherein the remaining delay budget information indicates at least one remaining delay budget and at least one associated buffer size.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a substrate, a semiconductor element, at least one connecting element, and an encapsulant. The semiconductor element is mounted to the substrate. The connecting element is disposed on the substrate and adjacent to the semiconductor element. The encapsulant covers at least a portion of the semiconductor element and at least a portion of the connecting element and defines at least one first groove surrounding the connecting element.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an upper surface, a semiconductor device mounted to the substrate, and a molding compound covering the lateral surface and the upper surface of the substrate and at least a portion of the semiconductor device. A surface of the semiconductor device is substantially coplanar with a surface of the molding compound.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate having a lateral surface and an upper surface, a semiconductor device mounted to the substrate, and a molding compound covering the lateral surface and the upper surface of the substrate and at least a portion of the semiconductor device. A surface of the semiconductor device is substantially coplanar with a surface of the molding compound.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal conductive element and a molding compound. The semiconductor device is mounted to the substrate. The thermal conductive element is disposed above the semiconductor device. The molding compound covers a side surface of the substrate and at least a part of a side surface of the semiconductor device.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal conductive element and a molding compound. The semiconductor device is mounted to the substrate. The thermal conductive element is disposed above the semiconductor device. The molding compound covers a side surface of the substrate and at least a part of a side surface of the semiconductor device.

Abstract: The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a substrate, a semiconductor element, at least one connecting element, and an encapsulant. The semiconductor element is mounted to the substrate. The connecting element is disposed on the substrate and adjacent to the semiconductor element. The encapsulant covers at least a portion of the semiconductor element and at least a portion of the connecting element and defines at least one first groove surrounding the connecting element.