Abstract: An image sensor includes a group of sensor units and a color filter layer disposed within the group of sensor units. The image sensor further includes a dielectric structure and a plurality of polarization splitters disposed corresponding to the color filter layer. Each of the plurality of polarization splitters has a first meta element extending in a first direction from top view and a second meta element extending in a second direction from top view. The second direction is perpendicular to the first direction.

Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed under a well portion, a second source/drain region disposed adjacent the first source/drain region, a dielectric material disposed between the first and second source/drain regions, and a conductive contact having a first portion disposed under the first source/drain region and a second portion disposed adjacent the first source/drain region. The second portion is disposed in the dielectric material. The structure further includes a conductive feature disposed in the dielectric material, and the conductive feature is electrically connected to the conductive contact. The conductive feature has a top surface that is substantially coplanar with a top surface of the well portion.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: An image sensor includes a photoelectric conversion layer, a plurality of deep trench isolations, a first color filter, a first deflector, and a covering layer. The photoelectric conversion layer includes a first photodiode and a second photodiode. The deep trench isolations separate the first photodiode and the second photodiode, in which a pixel dimension is determined by a distance between two adjacent deep trench isolations. The first color filter is disposed on the first photodiode and the second photodiode. The first deflector is disposed on the first color filter. The covering layer covers and surrounds the first deflector. A refractive index of the covering layer is greater than a refractive index of the first deflector, and a difference value between the refractive index of the covering layer and the refractive index of the first deflector is in a range from 0.15 to 0.6.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a nonconductive support element. The first radiation element has a feeding point. The second radiation element is coupled to the first radiation element. The third radiation element is coupled to a ground voltage and adjacent to the first radiation element. The fourth radiation element is coupled to the first radiation element. The fifth radiation element is coupled to the ground voltage and adjacent to the second radiation element. The first radiation element, the second radiation element, the third radiation element, and the fourth radiation element are at least partially surrounded by the fifth radiation element. The first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element are disposed on the nonconductive support element.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a feeding point. The second radiation element is coupled to the first radiation element. The third radiation element is coupled to a first grounding point. The third radiation element is further coupled through the fourth radiation element to a second grounding point. The fifth radiation element is coupled to the third radiation element and the fourth radiation element. The fifth radiation element is adjacent to the second radiation element. The first radiation element and the second radiation element are at least partially surrounded by the third radiation element, the fourth radiation element, and the fifth radiation element.

Abstract: An image sensor includes groups of sensor units, and a color filter layer having color units that disposed within the groups of sensor units, respectively. The color units of the color filter layer include a yellow color unit or a white color unit. The image sensor further includes a dielectric structure disposed on the color filter layer, and a meta surface disposed on the dielectric structure.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a first color filter segment and a second color filter segment adjacent to the first color filter segment. The first color filter segment and the second color filter segment correspond to different colors. The solid-state image sensor further includes a light-splitting structure disposed in the first color filter segment or the second color filter segment and a grid structure disposed between the first color filter segment and the second color filter segment. The light-splitting structure is separated from the grid structure.

Abstract: An image sensor includes a sensor unit, a sensing portion disposed within the sensor unit, and an isolation structure corresponding to the sensing portion. The isolation structure includes a first deep trench isolation (DTI) structure surrounding the sensor unit from top view, and a second deep trench isolation structure laterally enclosed by the first deep trench isolation structure. The second deep trench isolation structure is located close to a corner of the sensor unit defined by the first deep trench isolation structure. The second deep trench isolation structure is asymmetrical with respect to a horizontal middle line or a vertical middle line within the sensor unit.

Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a gate dielectric layer over a semiconductor substrate; depositing a work function layer over the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the work function layer comprises a metal element and a nonmetal element, and the ALD process comprises a plurality of cycles. Each of the cycles comprises: introducing a precursor gas comprising the metal element to a chamber to form a precursor surface layer on the semiconductor substrate in the chamber; purging a remaining portion of the precursor gas away from the chamber; performing a reactive-gas plasma treatment using a reactive-gas plasma comprising the nonmetal element to convert the precursor surface layer into a monolayer of the work function layer; purging a remaining portion of the reactive-gas plasma away from the chamber, and performing an inert-gas plasma treatment in the chamber.