Patents by Inventor Chun-Yung Cho
Chun-Yung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11455931Abstract: A source driving circuit of a display includes a gamma resistor strings, a digital to analog (DAC) circuit, and an output buffer circuit. The output buffer circuit includes input stage module, gain stage module, and output stage module. The input stage module includes main input stage unit and auxiliary input stage unit. Sizes of elements in main input stage unit are larger than sizes of elements in the auxiliary input stage unit, smaller sizes presenting smaller parasitic capacitances. During the switching period, the auxiliary input stage unit, gain stage module, and output stage module form a first unity gain amplifier outputting the driving voltages. During the stable period, the main input stage unit, gain stage module, and output stage module form a second unity gain amplifier outputting the driving voltages. A display device is also disclosed.Type: GrantFiled: March 2, 2022Date of Patent: September 27, 2022Assignee: Fitipower Integrated Technology, Inc.Inventors: Li-Wei Liu, Bo-Wen Huang, Chun-Yung Cho
-
Patent number: 11069586Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.Type: GrantFiled: December 15, 2015Date of Patent: July 20, 2021Assignee: Novatek Microelectronics Corp.Inventors: Jhih-Siou Cheng, Chun-Yung Cho, Po-Yu Tseng
-
Patent number: 10770011Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a first polarity buffer, a negative polarity buffer. The first polarity buffer receives a first supply voltage and a second supply voltage to output a first reference voltage to a first resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.Type: GrantFiled: May 2, 2018Date of Patent: September 8, 2020Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Chieh-An Lin, Chun-Yung Cho, Jhih-Siou Cheng
-
Publication number: 20180254012Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a first polarity buffer, a negative polarity buffer. The first polarity buffer receives a first supply voltage and a second supply voltage to output a first reference voltage to a first resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.Type: ApplicationFiled: May 2, 2018Publication date: September 6, 2018Applicant: NOVATEK MICROELECTRONICS CORP.Inventors: Chieh-An LIN, Chun-Yung CHO, Jhih-Siou CHENG
-
Patent number: 9997119Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a positive polarity buffer, a negative polarity buffer. The positive polarity buffer receives a first supply voltage and a second supply voltage to output a positive reference voltage to a positive resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.Type: GrantFiled: July 24, 2014Date of Patent: June 12, 2018Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Chieh-An Lin, Chun-Yung Cho, Jhih-Siou Cheng
-
Publication number: 20170092572Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.Type: ApplicationFiled: December 15, 2015Publication date: March 30, 2017Inventors: Jhih-Siou Cheng, Chun-Yung Cho, Po-Yu Tseng
-
Patent number: 9569989Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.Type: GrantFiled: June 26, 2013Date of Patent: February 14, 2017Assignee: Novatek Microelectronics Corp.Inventors: Ju-Lin Huang, Jhih-Siou Cheng, Chun-Yung Cho, Chieh-An Lin
-
Patent number: 9514666Abstract: A display driving module including a driving circuit portion and a non-driving circuit portion is provided. The driving circuit portion is controlled by a system circuit block. The driving circuit portion includes driving channels for driving a display panel. First ESD protection devices are disposed in the driving circuit portion corresponding to the driving channels for providing at least one discharge path. The non-driving circuit portion electrically connects the system circuit block, the driving circuit portion and the display panel. At least one of second ESD protection devices is disposed in at least one of the driving circuit portion, the non-driving circuit portion, the system circuit block and the display panel corresponding to the first ESD protection devices. The second ESD protection devices cooperate with the first ESD protection devices to provide the discharge path. An image display system including the foregoing display driving module is also provided.Type: GrantFiled: March 12, 2015Date of Patent: December 6, 2016Assignee: Novatek Microelectronics Corp.Inventors: Ju-Lin Huang, Jhih-Siou Cheng, Chun-Yung Cho, Chia-En Wu
-
Patent number: 9467108Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.Type: GrantFiled: June 17, 2015Date of Patent: October 11, 2016Assignee: Novatek Microelectronics Corp.Inventors: Chieh-An Lin, Chun-Yung Cho, Ju-Lin Huang
-
Patent number: 9270112Abstract: A driving circuit includes several first electrostatic current limiting resistors and several digital to analog converter (DAC) units. First ends of these first electrostatic current limiting resistors common coupled to a global path to receive a reference voltage. These DAC units respectively coupled to second ends of the first electrostatic current limiting resistors one-on-one to receive the reference voltage through the first electrostatic current limiting resistors.Type: GrantFiled: April 18, 2013Date of Patent: February 23, 2016Assignee: Novatek Microelectronics Corp.Inventors: Ju-Lin Huang, Che-Lun Hsu, Jhih-Siou Cheng, Chun-Yung Cho
-
Patent number: 9245857Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.Type: GrantFiled: June 1, 2015Date of Patent: January 26, 2016Assignee: Novatek Microelectronics corp.Inventors: Jhih-Siou Cheng, Tzu-Chiang Lin, Chia-En Wu, Chun-Yung Cho, Cheng-Hung Chen, Ju-Lin Huang
-
Publication number: 20150339960Abstract: A display driving module including a driving circuit portion and a non-driving circuit portion is provided. The driving circuit portion is controlled by a system circuit block. The driving circuit portion includes driving channels for driving a display panel. First ESD protection devices are disposed in the driving circuit portion corresponding to the driving channels for providing at least one discharge path. The non-driving circuit portion electrically connects the system circuit block, the driving circuit portion and the display panel. At least one of second ESD protection devices is disposed in at least one of the driving circuit portion, the non-driving circuit portion, the system circuit block and the display panel corresponding to the first ESD protection devices. The second ESD protection devices cooperate with the first ESD protection devices to provide the discharge path. An image display system including the foregoing display driving module is also provided.Type: ApplicationFiled: March 12, 2015Publication date: November 26, 2015Inventors: Ju-Lin Huang, Jhih-Siou Cheng, Chun-Yung Cho, Chia-En Wu
-
Publication number: 20150280664Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.Type: ApplicationFiled: June 17, 2015Publication date: October 1, 2015Inventors: Chieh-An Lin, Chun-Yung Cho, Ju-Lin Huang
-
Publication number: 20150262943Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Inventors: Jhih-Siou Cheng, Tzu-Chiang Lin, Chia-En Wu, Chun-Yung Cho, Cheng-Hung Chen, Ju-Lin Huang
-
Publication number: 20150228234Abstract: A buffer circuit, a display module, and a display driving method are disclosed. The buffer circuit comprises a positive polarity buffer, a negative polarity buffer. The positive polarity buffer receives a first supply voltage and a second supply voltage to output a positive reference voltage to a positive resistance string. The second supply voltage is less than the first supply voltage. The negative polarity buffer receives the second supply voltage and a third supply voltage to output a negative reference voltage to a negative resistance string. The third supply voltage is less than the second supply voltage.Type: ApplicationFiled: July 24, 2014Publication date: August 13, 2015Applicant: NOVATEK MICROELECTRONICS CORP.Inventors: Chieh-An LIN, Chun-Yung CHO, Jhih-Siou CHENG
-
Patent number: 9106189Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.Type: GrantFiled: September 2, 2013Date of Patent: August 11, 2015Assignee: Novatek Microelectronics Corp.Inventors: Chieh-An Lin, Chun-Yung Cho, Ju-Lin Huang
-
Patent number: 9048243Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.Type: GrantFiled: November 12, 2012Date of Patent: June 2, 2015Assignee: Novatek Microelectronics Corp.Inventors: Jhih-Siou Cheng, Tzu-Chiang Lin, Chia-En Wu, Chun-Yung Cho, Cheng-Hung Chen, Ju-Lin Huang
-
Patent number: 8917121Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.Type: GrantFiled: December 17, 2012Date of Patent: December 23, 2014Assignee: NOVATEK Microelectronics Corp.Inventors: Ju-Lin Huang, Keko-Chun Liang, Chun-Yung Cho, Cheng-Hung Chen
-
Publication number: 20140218111Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.Type: ApplicationFiled: September 2, 2013Publication date: August 7, 2014Applicant: Novatek Microelectronics Corp.Inventors: Chieh-An Lin, Chun-Yung Cho, Ju-Lin Huang
-
Patent number: RE47432Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.Type: GrantFiled: June 20, 2016Date of Patent: June 11, 2019Assignee: NOVATEK Microelectronics Corp.Inventors: Ju-Lin Huang, Keko-Chun Liang, Chun-Yung Cho, Cheng-Hung Chen