Abstract: A display driver integrated circuit structure includes first and second chips. The first chip includes first semiconductor devices including a scan driver, a data driver, a gamma adjuster, a power circuit, an OTP memory, a MTP memory, a digital I/O circuit, an analog I/O circuit, and a power I/O circuit. The second chip includes second semiconductor devices including a panel display controller, a power controller, a high-speed interface controller, a high-speed interface receiver, a high-speed interface command decoder, a low-speed interface controller, a low-speed interface receiver, a low-speed interface command decoder, a register read controller, a register write controller, a SRAM controller, a SRAM bit-cell, an OTP memory controller, a MTP memory controller, an OTP memory bit-cell, a MTP memory bit-cell, a shift register of the scan driver, a shift register of the data driver, a latch of the scan driver, and a latch of the data driver.

Abstract: The present invention provides an ESD protection circuit including a BOX device and at least one ESD device. The BOX device includes a BOX layer placed between a substrate and an active silicon layer, and the BOX device and the ESD device are connected in cascode. The ESD protection circuit has a higher trigger voltage and will not be falsely triggered, and an active layer of the BOX device does not form any parasitic paths with the underlying layers.

Abstract: A positive hysteresis elimination comparison circuit and a motor driver having a positive hysteresis elimination comparison circuit are provided. The motor driver includes a comparator and a hysteresis switching circuit. The comparator compares a voltage of a first voltage signal received by a first input terminal of the comparator with a voltage of a second voltage signal received by a second input terminal of the comparator to output a comparing signal within a comparison time. When the voltage of the first voltage signal is lower than the voltage of the second voltage signal, the comparison time is delayed. When the voltage of the first voltage signal is higher than the voltage of the second voltage signal and a positive hysteresis elimination signal is received by a first control terminal of the comparator, the comparison time is not delayed.

Abstract: A positive hysteresis elimination comparison circuit and a motor driver having a positive hysteresis elimination comparison circuit are provided. The motor driver includes a comparator and a hysteresis switching circuit. The comparator compares a voltage of a first voltage signal received by a first input terminal of the comparator with a voltage of a second voltage signal received by a second input terminal of the comparator to output a comparing signal within a comparison time. When the voltage of the first voltage signal is lower than the voltage of the second voltage signal, the comparison time is delayed. When the voltage of the first voltage signal is higher than the voltage of the second voltage signal and a positive hysteresis elimination signal is received by a first control terminal of the comparator, the comparison time is not delayed.

Abstract: A semiconductor structure including device structures arranged in a stack is provided. The device structures include substrates and through-substrate vias (TSVs). The TSVs are located in the substrates. The TSVs includes first TSVs. Each of the device structures includes the corresponding substrate and the corresponding first TSV. Each of the first TSVs passes through the corresponding substrate. The number of the TSVs in the endmost device structure is less than the number of the TSVs in another of the device structures. The first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.

Abstract: A 3D road scene generation system (1) for simulating a real environment is presented. The 3D road scene generation system (1) generates 3D topographic data (41) based on a topographic map (40) , generates 3D route data including a target route (43) based on road network data (42) , generates 3D landscape data (44) based on landscape data, and executes an integrating process on these data to generate the 3D road scene data (46, 49) for presenting terrain changes and scenery along the target route (43) .

Abstract: A training course recommendation device and a training course recommendation method are provided. The training course recommendation device includes a course database, a rider database, and a course recommendation processing module. The course database is configured to store a plurality of riding training courses. The rider database is configured to store rider characteristic data and riding sensing data. The course recommendation processing module is configured to analyze the rider characteristic data and the riding sensing data to obtain a user riding characteristic vector, compare the user riding characteristic vector and a course characteristic vector of each of the plurality of riding training courses to obtain a plurality of matching values of the plurality of riding training courses, and set at least one recommendation course from the plurality of riding training courses according to the matching value(s) which is(are) greater than a threshold.

Abstract: A cycling sport training suggestion system (10) includes a sport real-time analysis module (102), a cyclist information module (104), a route feature module (106) and a sport role data base (108). The cyclist information module (104) transmits a cyclist real-time sense information (110) to the sport real-time analysis module (102). The route feature module (106) transmits a route feature information (112) to the sport real-time analysis module (102). The sport role data base (108) transmits a cyclist historical sport information (114) and a perfect cyclist sport information (116) to the sport real-time analysis module (102). The sport real-time analysis module (102) integrates and analyzes the cyclist real-time sense information (110), the route feature information (112), the cyclist historical sport information (114) and the perfect cyclist sport information (116) to generate a cycling sport training suggestion signal (118).

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A cycling sport performance level analysis system includes an artificial intelligence classification analysis module, a bicycle apparatus, a classification knowledge rule module and a cyclist information module. The classification knowledge rule module transmits a classification test task rule including a track information to the artificial intelligence classification analysis module and the bicycle apparatus. The bicycle apparatus performs the classification test task rule and collects a sport sensing information which is sensed to transmit the sport sensing information to the artificial intelligence classification analysis module. The cyclist information module transmits a cyclist basic information and a track historical riding information to the artificial intelligence classification analysis module.

Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.

Abstract: A speed generation method for simulating riding is provided. A computer device (20) retrieves a riding weight and road condition information, selects one of a plurality of preset gear ratios (30) as a selected gear ratio, retrieves a wheel rotating speed of a bicycle (4), and determines a simulated speed in a simulating riding service based on the selected gear ratio, a tire parameter, and the rotating speed.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.

Abstract: A radio frequency energy-harvesting apparatus is applied to a radio frequency energy-transmitting apparatus with a location detection function. The radio frequency energy-harvesting apparatus includes a direct current signal receiving-processing unit, a rectification and harmonic generation unit, and a radar wave receiving-transmitting unit. The rectification and harmonic generation unit is electrically connected to the direct current signal receiving-processing unit. The radar wave receiving-transmitting unit is electrically connected to the rectification and harmonic generation unit.

Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.

Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.

Abstract: An RF energy transmitting apparatus with positioning and polarization tracing function is used for an RF energy harvesting apparatus. The RF energy transmitting apparatus includes a power radar transmitter and a radar controller. The power radar transmitter receives a power source signal and emits an electromagnetic source wave. The radar controller is electrically connected to power radar transmitter and receives a reflected harmonic wave. The power radar transmitter emits the electromagnetic source wave to scan a space. The RF energy harvesting apparatus generates and emits the reflected harmonic wave. The radar controller determines a position and a polarization angle of the RF energy harvesting apparatus after receiving the reflected harmonic wave and to adjust a polarization angle of the power radar transmitter to be within a predetermined angle range with respect to the polarization angle of the reflected harmonic wave sent from the RF energy harvesting apparatus.

Abstract: An operation mode control method implemented by a radar system, the operation mode control method includes steps of: (S1) receiving a single target tracking (STT) triggering data comprising a representation of triggering of a STT tracking mode and a selected tracking target to be tracked by the radar system; (S2) controlling a radar sensor to emit detection wave beam; (S3) controlling, the radar sensor to receive echo waves; (S4) analyzing, echo signal to generate STT target data; (S5) executing a STT program to obtain a tracking data of a selected tracking target; (S6) outputting the tracking data to a memory device for storage or to a human-machine interface (HMI) device for presenting to the user of the radar system.

Abstract: A signal receiving device includes a first amplifier, a duty cycle adjuster and a common mode feedback circuit. The first amplifier receives an input signal, a reference voltage and a bias voltage. The first amplifier generates a first common current based on the bias voltage and, based on the first common current, generates a first output signal and a second output signal complementary to each other by comparing the input signal and the reference voltage. The duty cycle adjuster charges and discharges a selected capacitor according to the first output signal or the second output signal to generate a sensing voltage, and generates a common reference voltage according to the sensing voltage. The common mode feedback circuit generates the bias voltage by comparing the common reference voltage and the reference voltage.