Patents by Inventor Chune-Sin Yeh

Chune-Sin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hot carrier effect simulation for integrated circuits
    Patent number: 6278964
    Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 21, 2001
    Assignees: Matsushita Electric Industrial Co., Ltd., BTA Technology Inc.
    Inventors: Jingkun Fang, Hirokazu Yonezawa, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
  • Low capacitance and low V.sub.t annular MOSFET design for phase lock loop applications
    Patent number: 5668392
    Abstract: Low capacitance, low threshold voltage annular MOSFET transistors are disclosed. Both low junction capacitance and low threshold voltage are achieved without degradation of drain current due to application of back-bias to the substrate upon which the transistor is formed. A polysilicon annulus, rather than the drain region, abuts field oxide regions, thereby preventing junction capacitance at interface of field oxide and drain (or source). Annular MOSFETs can be fabricated using conventional CMOS processing technology.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: September 16, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Chuck Huang, Chune-Sin Yeh