Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

Abstract: A hinge device includes a pivot seat, a rotating shaft, a first friction block, and a locking assembly. By being structurally provided with a sleeve, a first cam ring, a first elastic ring, a second friction block, a second cam ring, a second elastic ring, an elastic element, a locking portion, and a cover of the locking assembly, the hinge device has a locking function and a long service life.

Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: A wafer holder for generating a stable bias voltage, which mainly includes a holder, a ring member, and a cover ring, wherein a supporting surface of the holder is used to carry at least one wafer, and the ring member is arranged on the holder and located around the supporting surface and the wafer. The ring member includes an outer surface and an inner surface, wherein the inner surface of the ring member covers a part of the side surface of the holder and makes parts of the side surface exposed. When the cover ring is connected to the ring member, a shielding portion of the cover ring will cover the exposed side surface of the holder to avoid a film being formed on the exposed side surface of the holder to facilitate the formation of a uniform and stable bias voltage on the wafer holder.

Abstract: A masking structure for a wafer supporting plate comprises a cavity; a carrying tray having a plurality of recesses in a top surface thereof for receiving a plurality of wafers; the carrying tray can be transferred into and out of the cavity by using a robot; a supporting plate installed within the cavity and below the carrying tray; the supporting plate could move upwards, and downwards; a mask installed within the cavity and above the carrying tray; the mask formed with a plurality of through holes which are positioned and shaped to be corresponding to those of the wafers on the carrying tray; therefore, when the supporting plate lifts the carrying tray to be near the mask, the wafers are exposed out of the through holes.

Abstract: A vapor reduction device for a semiconductor wafer has a plurality of heat plates which are spaced arranged longitudinally for receiving a plurality of wafers, the heat plates are integrated into a heating frame which is further placed into a casing. The movements of the heat plates within the casing causes that the wafers can be heated rapidly and uniformly so as to evaporated vapor effectively. The heat plates are separable from the heating frame and thus a number of the heat plates is selectable as desired. The heating temperature for the heat plates is controllable independently so that the temperatures of the wafers are controllable so that the temperature differences of the wafers are controllable to be uniformly distributed.

Abstract: A plasma etching reaction chamber includes a casing having a receiving chamber; a base liftably installed below the receiving chamber; a first electrode and a second electrode; and a radio frequency electrode rod. The second electrode has a plurality of water channels and a bottom of the second electrode is installed with two cooling water tubes which are communicated with the plurality of water channels; upper sides of the two cooling water tubes are hidden within the driving rod and lower sides thereof extend downwards to be out of the casing so that external cooling water can flow into the cooling water tubes and then to the water channels to achieve the object of cooling.

Abstract: An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes an anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL.

Abstract: An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes an anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL.

Abstract: An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes an anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL.

Abstract: An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes a anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL.