Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

Abstract: An image sensor module includes a sensing surface, a filter element and a first anti-reflective microstructure, wherein the filter element faces towards the sensing surface, and the first anti-reflective microstructure is disposed on the sensing surface. The filter element includes a substrate, an optical deposition layer structure and an optical coating layer, wherein the optical deposition layer structure is disposed on a side of the substrate away from the sensing surface, and the optical coating layer and the optical deposition layer structure are correspondingly disposed on a side of the substrate facing towards the sensing surface. The optical deposition layer structure is multilayer. An air layer is formed between the first anti-reflective microstructure and the filter element, and the first anti-reflective microstructure and the air layer partially overlap at a direction vertical to the sensing surface.

Abstract: A static random-access memory (SRAM) circuit and associated read operation method and write operation method are provided. The SRAM circuit includes memory units arranged in M columns and N rows, M bit lines, N row-voltage selection lines, N word lines, and a control circuit. The control circuit includes a controller, a voltage source, a voltage selection module, a word-line driving module, and a bit-line driving module. The voltage source provides a first voltage and a second voltage. When the control circuit performs access to the memory unit located in the mth column and the nth row, the voltage selection module transmits one of the first voltage and the second voltage to an nth row-voltage selection line. The voltage selection module transmits the second voltage to the other (N?1) row-voltage selection lines. The variables M, N, m, and n are positive integers.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A knob structure for adjusting a sound parameter is provided, which includes a knob, an encoder, an interference component and a switching module. The knob has a shaft portion and an internal teeth portion. The encoder is connected to the shaft portion of the knob, in which the encoder includes a turntable and a bottom plate. The turntable has one or more protrusions in contact with the bottom plate. When the knob is rotated to rotate the turntable of the encoder, the one or more protrusions rub against the bottom plate. The interference component has a first end adjacent to the internal teeth portion of the knob. The switching module is configured to make the first end of the interference component be in contact with or moved away from the internal teeth portion of the knob. A headphone including the knob structure is also provided.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: Disclosed is a method for training a graphics processing neural network with a patch-based approach, which involves calculating an overlapping size and an invalid size of an output of each of at least one of multiple feature extraction layers of the graphic processing neural network according to a predetermined cropping scheme, dividing an input image into first patches in the forward pass and the first gradients into second patches in the backward pass to run streamline operation of the first and second patches. Before training, each first patch overlaps neighboring first patches at adjacent edges. In the forward pass, an invalid portion of the output of each of the at least one of the feature extraction layers cropped out based on the predetermined cropping scheme and a corresponding invalid size. Such method secures streamline operation in favor of enhanced memory utilization in training and accurate model prediction.

Abstract: A method of displaying a rear-view image and a digital dashboard using the method are provided. The method includes: receiving a rear-view image; and displaying the rear-view image on a default area of a display in response to receiving a signal associated with a direction indicator light, wherein the default area corresponds to the direction indicator light.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.

Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: A solid-state drive (SSD) controller is operable to determine whether M supply voltage(s) supplied to a NAND flash memory is correct. The SSD controller includes: a voltage detector configured to receive the M supply voltage(s) and thereby generate a detection result, wherein the M is a positive integer; a voltage inquiry module configured to output an inquiry signal to the NAND flash memory and thereby receive a response signal from the NAND flash memory, and configured to generate an inquiry result according to the response signal, wherein the inquiry result indicates M specified supply voltage(s) applicable to the NAND flash memory; and a voltage decision module configured to receive the detection result and the inquiry result, and configured to determine whether the M supply voltage(s) is/are equivalent to the M specified voltage(s) according to the detection result and the inquiry result and thereby generate a decision result.