Patents by Inventor Chung An Chen
Chung An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250111156Abstract: A text processing method includes: receiving text for describing a process of a task; obtaining a first sub-sentence group from the text for describing the process of the task, the first sub-sentence group including a plurality of sub-sentences arranged in an order in which the process occurs, and each of the plurality of sub-sentences including a workflow component; determining a workflow label corresponding to each sub-sentence in the first sub-sentence group; generating the workflow of the task based on the workflow labels corresponding to the plurality of sub-sentences in the first sub-sentence group; and generating a visual representation of the generated workflow for display by the workflow generation application.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Inventors: Peyvand Teymoori, Chung-Man Abelard Chow, JinRong Luo, Ming Chen, Qimeng Wei
-
Patent number: 12267029Abstract: A method of obtaining a parameter of a synchronous motor is disclosed and includes: setting an operating current of the motor; providing a positive fixed voltage to the motor and monitoring a feedback current from the motor; recording a triggering time for the feedback current to reach the operating current; providing a negative fixed voltage to the motor for the triggering time; obtaining a square-wave voltage with a fixed frequency based on the positive fixed voltage and the negative fixed voltage being provided; providing the square-wave voltage with the fixed frequency to one axis of the motor; transforming three-phase current from the motor into an axial current; computing an inductance value of this axis based on the fixed frequency, the square-wave voltage and the axial current; and, creating an inductance-current parameter table based on a plurality of the inductance values and the axial currents correspondingly.Type: GrantFiled: January 18, 2023Date of Patent: April 1, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Yen-Yang Chen, Jen-Chih Tseng, Lei-Chung Hsing
-
Patent number: 12265112Abstract: A three-terminal power line fault location and correction system and method, and a computer readable storage medium. An electronic device is electrically connected with a plurality of terminal devices. When a fault occurs at a certain position of the power line, each terminal device detects the fault to generate a fault distance corresponding to the fault. The electronic device corrects the fault distance as follows: the corrected fault distance of one of the terminal devices=(an actual distance between the terminal device and a divergence point+a function of actual distances between the other two terminal devices and the divergence point)*the fault distance corresponding to the terminal device/(the fault distance corresponding to the terminal device+the fault distance corresponding to a function of the actual distances between the other two terminal devices and the divergence point).Type: GrantFiled: July 14, 2022Date of Patent: April 1, 2025Assignee: TAIWAN POWER COMPANYInventors: Jui-Nien Chou, Shun-Pin Chen, Jen-Chung Chen
-
Patent number: 12265201Abstract: A light-emitting device array includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. A first beam shaping structure of the first light-emitting device is configured to convert light emitted by a first light-emitting structure of first light-emitting device into first structured light. A second beam shaping structure of the second light-emitting device is configured to convert light emitted by a second light-emitting structure of second light-emitting device into second structured light. Speckle patterns and spatial distributions of the first structured light and the second structured light on a projection plane are the same. A third beam shaping structure of the third light-emitting device is configured to convert light emitted by a third light-emitting structure of third light-emitting device into third structured light.Type: GrantFiled: September 7, 2023Date of Patent: April 1, 2025Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jun-Da Chen, Yu-Heng Hong, Wen-Cheng Hsu, Tzu-Hsiang Lan, Hao-Chung Kuo
-
Patent number: 12265553Abstract: Provided herein are methods and systems for identifying a related data values in a plurality of datasets. The method can include extracting data from the plurality of datasets, identifying potential linking categories, and determining a validity of the potential linking categories. One or more linking categories can be selected from the potential linking categories based on the validity, and related data values can be identified between the plurality of datasets based on the selected linking categories. Also provided herein are methods and systems for classifying data values as reconciled or non-reconciled. The method can include identifying a plurality of related data values in a plurality of datasets. For each of the plurality of related data values, a similarity score and confidence score can be determined, and the plurality of related data values can be classified as reconciled or non-reconciled based on the similarity score and/or the confidence score.Type: GrantFiled: March 29, 2023Date of Patent: April 1, 2025Assignee: PwC Product Sales LLCInventors: Chung-Sheng Li, Winnie Cheng, Mark John Flavell, Nicholas John Hamer, Rhodri Davies, Thomas Vincent Giacomucci, Lacey A. Woolf, Raymund Anthony Florand Beltran, Craig Sharples, Matthew F. Connelly, Kevin Ma Leong, Scott Likens, Joseph David Voyles, Xiaoying Chen, Waqar Sarguroh, Nancy Alayne Lizotte
-
Patent number: 12267984Abstract: A heat dissipation assembly is disclosed and includes a frame and a fan. The frame includes a heat conduction channel and an airflow intake. The heat conduction channel is communication with an exterior through airflow intake. The frame includes a first plane, a second plane and an inclined plane. The first plane is disposed adjacent to the airflow intake. The inclined plane is connected between the first plane and the second plane. The second plane includes an inlet. The heat conduction channel is in communication between the airflow intake and the inlet. A cross-section area of the heat conduction channel adjacent to the airflow intake is greater than that of the heat conduction channel adjacent to the inlet. The fan is spatially corresponding to the inlet, and assembled with the frame to form an outlet in communication with the airflow intake and the heat conduction channel through the inlet.Type: GrantFiled: November 18, 2022Date of Patent: April 1, 2025Assignee: Delta Electronics, Inc.Inventors: Yi-Han Wang, Chao-Fu Yang, Chih-Chung Chen, Kuo-Tung Hsu, Meng-Yu Chen
-
Publication number: 20250101428Abstract: Small interfering RNAs (siRNA) having specific modification patterns to improve interference efficiencies thereof. The modification patterns each comprises a combination of 2?-O methyl modification, 2?-O-fluoro-modification, and phosphorothioate (PS) bonds at defined positions in the sense strand and anti-sense strand of each siRNA, and optionally 5? phosphate modifications.Type: ApplicationFiled: December 2, 2022Publication date: March 27, 2025Inventors: Yi-Chung CHANG, Chi-Fan YANG, Hui-Yu CHEN, Yi-Fen CHEN
-
Publication number: 20250106974Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih LAI, Han-Lung CHANG, Chi YANG, Shang-Chieh CHIEN, Bo-Tsun LIU, Li-Jui CHEN, Po-Chung CHENG
-
Publication number: 20250105019Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.Type: ApplicationFiled: December 10, 2024Publication date: March 27, 2025Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
-
Publication number: 20250102500Abstract: The present disclosure relates to a new process for construction of controlled structures on the surface of modified digital barcoded magnetic beads (BMB) with higher capacity, higher fluorescence intensity, wider dynamic range, and improved sensitivity in clinical applications.Type: ApplicationFiled: September 21, 2023Publication date: March 27, 2025Inventors: Chung-Jen Hou, Gao Chen
-
Publication number: 20250107234Abstract: A display device has a display area and a peripheral area, and includes an array substrate. The array substrate includes M number of pixel unit columns disposed in the display area and a first dummy electrode disposed in the peripheral area, where M is a positive integer greater than or equal to 2. The M number of pixel unit columns include a first pixel unit column to an Mth pixel unit column arranged in sequence. Each of the M number of pixel unit columns includes a plurality of pixel units arranged in sequence. The first dummy electrode is located on one side of the first pixel unit column. During a frame period, the first pixel unit column receives the first pixel signal, and the first dummy electrode receives the first dummy signal. The polarity of the first pixel signal is different from that of the first dummy signal.Type: ApplicationFiled: July 1, 2024Publication date: March 27, 2025Inventors: Chung-Lin CHANG, Hsuan-Chen LIU, Yu-Cheng LIN, Chen-Hao SU
-
Publication number: 20250104191Abstract: A detecting system includes a camera and a processor. The camera is configured to capture a first target object to generate a first image and is configured to capture a second target object different from the first target object to generate a second image. The processor is configured to detect the first image by using a first model to generate a first result and is configured to train the first model by using the first result. When the processor trains the first model by using the first result, the camera captures the second target object. After the camera captures the second target object, the processor further trains the first model by using the second image.Type: ApplicationFiled: December 15, 2023Publication date: March 27, 2025Inventors: Gan-Lin CHEN, Chun-Lin CHIEN, Chih-Chung CHIU, Chih-Ping HO
-
Publication number: 20250107207Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.Type: ApplicationFiled: December 9, 2024Publication date: March 27, 2025Inventors: Chi-Sheng LAI, Wei-Chung SUN, Yu-Bey WU, Yuan-Ching PENG, Yu-Shan LU, Li-Ting CHEN, Shih-Yao LIN, Yu-Fan PENG, Kuei-Yu KAO, Chih-Han LIN, Jing Yi YAN, Pei-Yi LIU
-
Patent number: 12260049Abstract: A touch light-emitting module having hallowed portion for incapsulation resin and a manufacturing method thereof are disclosed. The touch light-emitting module includes a printed circuit board and a touch-control conductor. The printed circuit board has a top surface on which a touch-control IC and a luminous unit that is electrically connected are disposed. The touch-control conductor includes a hollowed portion. The touch-control conductor is coated, on the bottom thereof, with a conductive material to combine with the top surface of the printed circuit board, so that the touch-control IC and the luminous unit are located in the hollowed portion. An encapsulation resin is then injected into a space between the printed circuit board and the hollowed portion to complete encapsulation. As such, the module offers a simplified structure to achieve an effect of minimization, and simplifies the manufacturing process and reduces the working time to thereby enhance the yield.Type: GrantFiled: January 29, 2024Date of Patent: March 25, 2025Assignee: LIGITEK ELECTRONICS CO., LTD.Inventors: Yi-Wen Chen, Wen-Chung Chou, I-Hsin Tung
-
Patent number: 12261188Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.Type: GrantFiled: April 17, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Ying Liao, Yu-Chu Lin, Chih Wei Sung, Shih Sian Wang, Chi-Chung Jen, Yu-chien Ku, Yen-Jou Wu, Huai-jen Tung, Po-Zen Chen
-
Publication number: 20250098271Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.Type: ApplicationFiled: December 4, 2024Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Wen Zhang, Kun-Chen Ho, Chun-Lung Chen, Chung-Yi Chiu, Ming-Chou Lu
-
Publication number: 20250098346Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.Type: ApplicationFiled: January 19, 2024Publication date: March 20, 2025Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
-
Publication number: 20250096000Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.Type: ApplicationFiled: October 16, 2023Publication date: March 20, 2025Applicant: United Microelectronics Corp.Inventors: Kun-Ju Li, Hsin-Jung Liu, Jhih Yuan Chen, I-Ming Lai, Ang Chan, Wei Xin Gao, Hsiang Chi Chien, Hao-Che Hsu, Chau Chung Hou, Zong Sian Wu
-
Publication number: 20250093745Abstract: An image sensor module includes a sensing surface, a filter element and a first anti-reflective microstructure, wherein the filter element faces towards the sensing surface, and the first anti-reflective microstructure is disposed on the sensing surface. The filter element includes a substrate, an optical deposition layer structure and an optical coating layer, wherein the optical deposition layer structure is disposed on a side of the substrate away from the sensing surface, and the optical coating layer and the optical deposition layer structure are correspondingly disposed on a side of the substrate facing towards the sensing surface. The optical deposition layer structure is multilayer. An air layer is formed between the first anti-reflective microstructure and the filter element, and the first anti-reflective microstructure and the air layer partially overlap at a direction vertical to the sensing surface.Type: ApplicationFiled: August 26, 2024Publication date: March 20, 2025Inventors: Tzu-Kan CHEN, Ti Lun LIU, Jih Chung HUANG, Yu-Pin WANG, Yu-Chen LAI, Ming-Ta CHOU
-
Publication number: 20250098273Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.Type: ApplicationFiled: December 4, 2024Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Wen Zhang, Kun-Chen Ho, Chun-Lung Chen, Chung-Yi Chiu, Ming-Chou Lu