Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Abstract: A magnetic element includes a first magnetic core, a second magnetic core, a first winding and a second winding. The first magnetic core includes a first lateral core part, a second lateral core part and a first middle core part between the first lateral core part and the second lateral core part. The second magnetic core includes a third lateral core part, a fourth lateral core part and a second middle core part between the third lateral core part and the fourth lateral core part. The third lateral core part is located beside the first middle core part. The second middle core part is located beside the second lateral core part. The first winding is wound around the first middle core part and the third lateral core part. The second winding is wound around the second middle core part and the second lateral core part.

Abstract: A broadband linear polarization antenna structure, including a reference conductive layer, a first patch antenna, a second patch antenna, and a feeding portion, is provided. The reference conductive layer includes through holes. A first short pin is connected between the reference conductive layer and the first patch antenna, and a second short pin is connected between the first patch antenna and the second patch antenna. Each feeding portion penetrates the reference conductive layer through the through hole and is coupled to the first patch antenna.

Abstract: A lithography system includes an immersion lithographic apparatus, a fluid supply device, and a sensor. The fluid supply is configured to supply fluid to the immersion lithographic apparatus. The fluid supply device includes at least one liquid storage tank, an upper liquid pipe and a lower liquid pipe connected to the liquid storage tank. The sensor includes at least one hydraulic pressure gauge. The at least one hydraulic pressure gauge is arranged near a lower part of the liquid storage tank and connected to the lower liquid pipe and the upper liquid pipe so as to measure the hydraulic pressure at a bottom of the liquid storage tank. The height of the liquid level in the liquid storage tank is calculated from the hydraulic pressure.

Abstract: A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate, in which the substrate is SiC base. The substrate, from bottom to top, sequentially includes an N-type heavy doping base layer, an N-type light doping layer, a P-well region, and an N-type heavy doping layer. The substrate is etched by using a patterned mask to form a gate trench and a channel region defined by the gate trench. The channel region is shielded by the patterned mask. An ion implant is performed to the gate trench such that a shielding implant layer is formed on the bottom of the gate trench. An oxidation process is performed to the gate trench thereby forming a gate oxide layer. The oxidation rate at the bottom of the gate trench is faster than the oxidation rate at the sidewall of the gate trench. A semiconductor device is also provided.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A system of generating data from diffusion-weighted images for pre-processing and a method thereof are disclosed. In the system, a processing parameter set including diffusion information is acquired; after a raw diffusion-weighted image including data images and image information is acquired, the image information is interpreted to set image processing data of the raw diffusion-weighted image, and non-deformation correction and deformation correction are performed on the raw diffusion-weighted image to generate a pre-processed diffusion-weighted image based on the processing parameter set and the image processing data. Therefore, the image processing data can be automatically set based on the raw diffusion-weighted image, to achieve the effect of lowering difficulty for analyzing DWI and saving setup time of image processing data.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: Disclosed herein is a recombinant baculovirus for producing an alphavirus virus-like replicon particle (VRP) having an exogenous gene in a mosquito cell. Said recombinant baculovirus comprises: (1) a replicon comprising a first promoter, and a first polynucleotide encoding at least one alphavirus non-structural protein and is operably linked to the first promoter; and (2) a helper comprising a second promoter, and a second polynucleotide encoding at least one alphavirus structural protein and is operably linked to the second promoter; wherein, the helper is upstream or downstream to the replicon; and the first promoter is less effective than the second promoter in driving gene expression in the mosquito cell. Also encompassed in the present disclosure are methods for detecting an antibody against an alphavirus in a biological sample, and/or screening an antiviral agent suitable for treating an alphavirus infection, with the aid of the alphavirus VRP produced by the present recombinant baculovirus.

Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: The invention discloses a digital signature system. The digital signature system comprises an electronic device and a data storage device. The electronic device generates a specific data by executing a specific operation, and performs a calculation operation on the specific data via a hash algorithm to generate a hash data. The data storage device comprises a controller, a plurality of flash memories, and a data transmission interface. The electronic device transmits the hash data to the data storage device via the transmission interface. The controller comprises a firmware. The firmware reads an unclonable function, and generates a private key according to the unclonable function, and encrypts the hash data by the private key to obtain a digital signature. The data storage device transmits the digital signature to the electronic device via the transmission interface.

Abstract: A package structure includes a first thermal dissipation structure. The first thermal dissipation structure includes a semiconductor substrate, conductive vias, a thermal transmission structure, first capacitors, bonding pads, and bonding vias. The conductive vias are embedded in the semiconductor substrate. The thermal transmission structure is disposed over the semiconductor substrate and the conductive vias. The thermal transmission structure includes a conductive plane. The first capacitors are at least partially embedded in the thermal transmission structure. The bonding pads and the bonding vias are embedded in the thermal transmission structure. The bonding vias electrically connect the conductive vias and the bonding pads. The conductive plane is in physical contact with sidewalls of at least one of the bonding pads.

Abstract: The present invention provides a residual current detection device comprising a first conductive wire, a second conductive wire, a first magnetic concentrator and a magnetic sensing device wherein the first conductive wire generates a first magnetic field, the second conductive wire is arranged at one side of the first conductive wire for generating a second magnetic field, the first magnetic concentrator is arranged between the first and second conductive wires whereby a highly concentrated magnetic field area is formed between the first and second conductive wires, and the magnetic sensing device is arranged in the highly concentrated magnetic field area for detecting the first and second magnetic fields.

Abstract: A light emitting diode (LED) package includes a substrate, at least one micro LED chip, a black material layer, and a transparent material layer. The substrate has a width ranging from 100 micrometers to 1000 micrometers. The at least one micro LED chip is electrically mounted on a top surface of the substrate and has a width ranging from 1 micrometer to 100 micrometers. The black material layer covers the top surface of the substrate to expose the at least one micro LED chip. The transparent material layer covers the at least one micro LED chip and the black material layer.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.