Patents by Inventor Chung An Wang

Chung An Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
  • Publication number: 20240145630
    Abstract: A light-emitting device includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer, and a second semiconductor layer which are disposed on the upper surface of the substrate in such order. The substrate has a substrate edge region surrounding and exposed from the epitaxial structure. The substrate edge region includes a first substrate edge region and a second substrate edge region which is more proximate to the epitaxial structure than the first substrate edge region. The first substrate edge region has a first uneven toothed surface or an even flat surface. The second substrate edge regions are formed with second uneven toothed surfaces which have a height greater than a height of the first even toothed surface, or the even flat surface.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Inventors: Minyou HE, Xiaoliang LIU, Qing WANG, Ling-Yuan HONG, Chung-Ying CHANG
  • Publication number: 20240145613
    Abstract: The present disclosure provides a silicon carbide (SiC) opto-thyristor and a method for manufacturing the same. The SiC opto-thyristor includes a SiC substrate, a SiC light emitter and a SiC light-sensitive thyristor. In the method, a SiC epitaxy is mainly formed on the SiC substrate with the doped P-type and N-type semiconductor materials to define the regions for forming the SiC light emitter and the basic structures of the SiC light-sensitive thyristor. A passivation layer is deposited. Conducting channels for the SiC light emitter and the SiC light-sensitive thyristor are formed by an etching process. After patterning a metal conductor layer, a structure of electrical contacts of the SiC light emitter and the SiC light-sensitive thyristor is formed. Then, terminals of an input voltage and an output voltage of the silicon carbide opto-thyristor are formed after a wire bonding process upon the electrical contacts. Finally, a packaging process is performed.
    Type: Application
    Filed: October 10, 2023
    Publication date: May 2, 2024
    Inventors: Di-Bao WANG, Wen-Chung LEE
  • Publication number: 20240143455
    Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.
    Type: Application
    Filed: May 15, 2023
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Lee Chung CHEN, Li Hao CHIANG, Gin CHI, Wei Jie HSU, Jiann Wen WANG, Wen Dwo HWANG
  • Patent number: 11969097
    Abstract: An inflatable product includes an inflatable chamber and a supplemental layer. The supplemental layer is disposed on the inflatable chamber. Further, the supplemental layer is directly or indirectly fixed to the inflatable chamber by sewing. The inflatable chamber is made of plastic. The material of the supplemental layer is different from that of the inflatable chamber.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 30, 2024
    Assignee: INNOVATOR PLASTIC & ELECTRONICS (HUIZHOU) CO LTD
    Inventors: Cheng-Chung Wang, Chien-Hua Wang, Yao-Hua Wang
  • Publication number: 20240137561
    Abstract: A three-dimensional data encoding method includes: obtaining geometry information which includes first three-dimensional positions on a measurement target, and is generated by a measurer that radially emits an electromagnetic wave in different directions and obtains a reflected wave which is the electromagnetic wave that is reflected by the measurement target; generating a two-dimensional image including first pixels corresponding to the directions, based on the geometry information; and encoding the two-dimensional image to generate a bitstream. Each of the first pixels has a pixel value indicating a first three-dimensional position or attribute information of a three-dimensional point which is included in a three-dimensional point cloud and corresponds to a direction to which the first pixel corresponds among the directions.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 25, 2024
    Inventors: Toshiyasu SUGIO, Noritaka IGUCHI, Pongsak LASANG, Chi WANG, Chung Dean HAN
  • Patent number: 11966628
    Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Han-Wen Hu, Yung-Chun Li, Huai-Mu Wang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20240125647
    Abstract: According to one embodiment, a sensor device comprises a sensor configured to output a sense signal, a value the sense signal changing over time based on incident light, a first reset circuit configured to set the value of the sense signal to a reset value when the value of the sense signal exceeds a threshold, a counter configured to count a first number of times of reset by the first reset circuit, and an arithmetic operation circuit configured to calculate an amount of incident light of a certain period based on the value of the sense signal, the reset value, and the first number of times of reset.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Applicant: Japan Display Inc.
    Inventors: Naoki TAKADA, Xingle WANG, Chung-Kai CHEN
  • Publication number: 20240126374
    Abstract: A method for touchless gesture recognition is provided. The method includes transmitting ultrasonic signals via a speaker. The method includes generating ultrasonic signals. The method includes receiving the reflected ultrasonic signals from an object via two or more microphones. The method includes computing a frequency shift according to the reflected ultrasonic signals. The method includes identifying a gesture that corresponds to a movement of the object according to the frequency shift. The method includes performing a function that corresponds to the gesture.
    Type: Application
    Filed: February 13, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Xuan XU, Ching-Lung CHAN, Shih-Chung WANG, Yen-Son Paul HUANG, Shih-Chin GONG
  • Publication number: 20240124298
    Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 18, 2024
    Inventors: Yun-Chung Wu, Jhao-Yi Wang, Hao Chun Yang, Pei-Wei Lee, Wen-Hsiung Lu
  • Publication number: 20240128178
    Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.
    Type: Application
    Filed: February 8, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
  • Publication number: 20240120295
    Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hsien Lee, Yun-Chung Wu, Pei-Wei Lee, Fu Wei Liu, Jhao-Yi Wang
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 11952639
    Abstract: A method for tempering steel for riveting includes positioning a first component having a first composition over a second component having a second composition, and resistance spot welding the first component to the second component using a resistance spot weld gun to form a spot weld. The method includes tempering at least one of the first component, the second component and the spot weld with the resistance spot weld gun, and coupling a third component having a third composition to the first component and the second component with a rivet, and the third composition is different than the first composition and the second composition.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: April 9, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Steven Cipriano, Pei-chung Wang, Zhenke Teng
  • Patent number: 11953373
    Abstract: According to one embodiment, a sensor device comprises a sensor configured to output a sense signal, a value the sense signal changing over time based on incident light, a first reset circuit configured to set the value of the sense signal to a reset value when the value of the sense signal exceeds a threshold, a counter configured to count a first number of times of reset by the first reset circuit, and an arithmetic operation circuit configured to calculate an amount of incident light of a certain period based on the value of the sense signal, the reset value, and the first number of times of reset.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Naoki Takada, Xingle Wang, Chung-Kai Chen
  • Patent number: 11955401
    Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Patent number: 11944970
    Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 2, 2024
    Assignees: INSTANT NANOBIOSENSORS, INC., INSTANT NANOBIOSENSORS CO., LTD.
    Inventors: Yu-Chung Huang, Yi-Li Sun, Ting-Chou Chang, Jhy-Wen Wu, Nan-Kuang Yao, Lai-Kwan Chau, Shau-Chun Wang, Ying Ting Chen
  • Publication number: 20240105664
    Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
  • Patent number: D1024806
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 30, 2024
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: James Siminoff, Mark D Siminoff, Wen-Yo Lu, Christopher Loew, Jia Li, Wei-Chung Wang, Gregory Berlin, Andrew Louis Russell
  • Patent number: D1024932
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: April 30, 2024
    Assignee: WALSIN LIHWA CORPORATION
    Inventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin