Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A secondary-side controller applied to a flyback power converter prevents a secondary side of the flyback power converter from conducting incorrectly. The secondary-side controller includes a first comparison circuit, a second comparison circuit, and a gate control signal generation circuit. The first comparison circuit generates a first comparison signal according to a drain voltage of a synchronous switch of the secondary side of the flyback power converter and a first parameter. The second comparison circuit generates a ready signal according to the first comparison signal and a resistance of an external resistor. The gate control signal generation circuit generates a gate control signal to the synchronous switch according the ready signal and the drain voltage, and the synchronous switch is turned on according to the gate control signal.

Abstract: A transistor comprises a colored light shielding layer over the semiconductor layer thereof. The colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm. The colored light shielding layer may have a white, black, red, yellow, or gray color. The colored light shielding layer can be formed from a metal oxide film, a p-type oxide semiconductor, or a perovskite. The colored light shielding layer reduces defects that may be generated in the semiconductor layer due to UV light exposure during the manufacturing process, improving device performance and reliability.

Abstract: Disclosed is the source active region.

Abstract: A packet identification system and a packet identification method are provided. The packet identification system receives a target packet, and includes a first packet header analyzer, a host, and a second packet header analyzer. The first packet header analyzer is configured to preset a plurality of first packet header formats, and identifies whether or not the target packet is one of a plurality of first packet types according to the first packet header formats. The host is configured to dynamically set at least one second packet header format. The second packet header analyzer is communicatively connected to the host. The second packet header analyzer is configured to store the at least one second packet header format, and identifies whether or not the target packet is at least one second packet type according to the at least one second packet header format.

Abstract: A chip comprises a plurality of signal receiving circuits, a transceiver circuit and a memory circuit. The plurality of signal receiving circuits are set at different locations on the chip. The transceiver circuit includes a dynamic switch circuit and a baseband processor. The dynamic switch circuit is configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits. The baseband processor is configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and obtain a data packet of an input radio-frequency signal received by an external antenna. The memory circuit is configured to store the frequency spectrum and magnitude of the to-be-analyzed signal, and transmit the frequency spectrum and magnitude to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.

Abstract: A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

Abstract: An automatic detection circuit for an integrated circuit and an automatic detection method for the same are provided. The automatic detection circuit is suitable for a system-on-chip (SoC). A control unit of the automatic detection circuit enters an automatic detection mode to: switch a first dynamic switching circuit to connect a main bus to a virtual host circuit; switch a second dynamic switching circuit to connect memory interfaces and intellectual property circuit to a virtual input and output circuit; send detection vectors to the virtual host circuit to set and activate the memory interfaces and the intellectual property circuits; send the detection vectors to the virtual I/O circuit to replace external memory and external equipment for sending and receiving signals; and compare signals received by the virtual host circuit or signals received by the virtual input and output circuit with predetermined signal data to generate a detection result.

Abstract: A method and a system for recording an integrated circuit version are provided. The method is adapted to a register in an integrated circuit, which includes the following steps: recording the integrated circuit version with N bits, in which N is an integer greater than 1; and amending only a bit value of at least one bit selected from the N bits that have not been used for denoting any past integrated circuit version each time when the integrated circuit is revised.

Abstract: An automatic detection circuit for an integrated circuit and an automatic detection method for the same are provided. The automatic detection circuit is suitable for a system-on-chip (SoC). A control unit of the automatic detection circuit enters an automatic detection mode to: switch a first dynamic switching circuit to connect a main bus to a virtual host circuit; switch a second dynamic switching circuit to connect memory interfaces and intellectual property circuit to a virtual input and output circuit; send detection vectors to the virtual host circuit to set and activate the memory interfaces and the intellectual property circuits; send the detection vectors to the virtual I/O circuit to replace external memory and external equipment for sending and receiving signals; and compare signals received by the virtual host circuit or signals received by the virtual input and output circuit with predetermined signal data to generate a detection result.

Abstract: The application discloses a router coupled to a first device and a second device. The router includes a first packet input interface, a second packet input interface, a first register, a second register, a control circuit and a switch module. The switch module includes a control port, a first packet output interface and a second packet output interface. The application further discloses a routing method. The router and routing method saves idle time and improves quality of service.

Abstract: An integrated circuit chip includes a core circuit, a first bond pad, a first switch circuit, a second configuration resistor, a control circuit, and a storage unit. The first bonding pad is coupled to a first external reference voltage through a first node, and the first node is coupled to the first external reference voltage through a bonding wire or a first configuration resistor. The first switch circuit is coupled between a first internal reference voltage and the first node. The second configuration resistor is coupled between the first internal reference voltage and the first switch circuit or between the first switch circuit and the first node. In a first mode, the control circuit turns on the first switch circuit, and writes a configuration state of the first bonding pad to the storage unit. In a second mode, the control circuit turns off the first switch circuit.

Abstract: A packet transmission control method used in a packet transmission circuit is provided that includes the steps outlined below. A packet receiving circuit, processing circuits and a packet sending circuit of the packet transmission circuit are kept in a non-operation status. The packet receiving circuit is woken up to the operation status to receive the packet stream and is restored to the non-operation status. The processing circuits are woken up to an operation status respectively according to an operation order thereof to receive, transmit and process the packet stream within a respective process time period and are restored to the non-operation status after the packet stream is processed. The packet sending circuit is woken up to the operation status to transmit the packet stream processed by the processing circuits to an external device and is restored to the non-operation status after the packet stream is transmitted.

Abstract: A voltage control circuit for controlling an operating voltage of a target circuit, including: a speed detecting circuit, configured to detect an operating speed of the target circuit; and a control circuit, coupled to the speed detecting circuit, configured to generate a voltage control signal according to a difference between the operating speed and a predetermined speed, to a power supply circuit which generates the operating voltage, to control the operating voltage.

Abstract: The application discloses a router coupled to a first device and a second device. The router includes a first packet input interface, a second packet input interface, a first register, a second register, a control circuit and a switch module. The switch module includes a control port, a first packet output interface and a second packet output interface. The application further discloses a routing method. The router and routing method saves idle time and improves quality of service.

Abstract: A voltage control circuit for controlling an operating voltage of a target circuit, including: a speed detecting circuit, configured to detect an operating speed of the target circuit; and a control circuit, coupled to the speed detecting circuit, configured to generate a voltage control signal according to a difference between the operating speed and a predetermined speed, to a power supply circuit which generates the operating voltage, to control the operating voltage.

Abstract: A packet transmission control method used in a packet transmission circuit is provided that includes the steps outlined below. A packet receiving circuit, processing circuits and a packet sending circuit of the packet transmission circuit are kept in a non-operation status. The packet receiving circuit is woken up to the operation status to receive the packet stream and is restored to the non-operation status. The processing circuits are woken up to an operation status respectively according to an operation order thereof to receive, transmit and process the packet stream within a respective process time period and are restored to the non-operation status after the packet stream is processed. The packet sending circuit is woken up to the operation status to transmit the packet stream processed by the processing circuits to an external device and is restored to the non-operation status after the packet stream is transmitted.

Abstract: An integrated circuit chip includes a core circuit, a first bond pad, a first switch circuit, a second configuration resistor, a control circuit, and a storage unit. The first bonding pad is coupled to a first external reference voltage through a first node, and the first node is coupled to the first external reference voltage through a bonding wire or a first configuration resistor. The first switch circuit is coupled between a first internal reference voltage and the first node. The second configuration resistor is coupled between the first internal reference voltage and the first switch circuit or between the first switch circuit and the first node. In a first mode, the control circuit turns on the first switch circuit, and writes a configuration state of the first bonding pad to the storage unit. In a second mode, the control circuit turns off the first switch circuit.

Abstract: The present invention provides an auto-detection control apparatus, which receives an electric power from one of a system power source signal and an external device and performs a detection when coupled to the external device. The apparatus comprises a detection module, a power management module and a control module. The detection module generates a first result based on whether a first power signal from the external device exists, wherein the first result is related to whether the external device provides an electricity to itself. The power management module prevents a conflict between the system power source signal and the first power signal. The control module determines whether the electric power is supplied to the external device by the power management module based on the first result.

Abstract: An integrated circuit includes: a circuit pin; a detecting circuit coupled to the circuit pin, and arranged to detect a signal level value of the circuit pin when the integrated circuit operates in a first operational mode; a storage circuit coupled to the detecting circuit, and arranged to store the signal level value; and a controlling circuit coupled to the storage circuit, and arranged to set a voltage level of the circuit pin according the signal level value when a processing circuit of the integrated circuit operates in a second operational mode.