Patents by Inventor Chung-Che Huang
Chung-Che Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935804Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
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Publication number: 20230218184Abstract: An optical sensor system and method of manufacture thereof can include: providing a sensor body; mounting a light emitter to the sensor body, the light emitter for emitting light into tissue; mounting a light detector to the sensor body for providing a physiological measurement from within the tissue; and affixing an optical film above the light detector, the light being angularly constrained by the optical film.Type: ApplicationFiled: September 21, 2021Publication date: July 13, 2023Inventors: Judy Lau Hermann, Sudhir Mulpuru, Chung-Che Huang
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Patent number: 10422836Abstract: A device for estimating a state-of-health (SOH) of a battery module controls a battery current to have a predetermined current value for a testing period such that a battery voltage decreases during the testing period, corrects a voltage variation value of the battery module during the testing period according to a temperature value of the battery module, and estimates the SOH of the battery module according to the corrected voltage variation value, a current variation value of the battery module during the testing period, and a rated capacity of the battery module.Type: GrantFiled: December 29, 2016Date of Patent: September 24, 2019Assignee: AUTOMOTIVE RESEARCH & TESTING CENTERInventors: Chung-Che Huang, Po-Hsu Lin, Zhi-Rong Wang
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Patent number: 10389167Abstract: A method for distributing power using multiple power sources is performed by a control device electrically connected to multiple rechargeable power units and a load. The control device creates an output power reference table according to multiple power setting values, output power ranges and battery efficiencies of the multiple rechargeable power units. The output power reference table includes the power setting values and power distribution information corresponding to the power setting values. When receiving a consumed power value of the load, the control device selects corresponding power setting value and power distribution information in the output power reference table and controls the multiple rechargeable power units to simultaneously output power to the load according to the power distribution information. By referring to the output power values of all the rechargeable power units and allocating power outputted from all the rechargeable power units, power utilization efficiency can be enhanced.Type: GrantFiled: December 26, 2017Date of Patent: August 20, 2019Assignee: Automotive Research & Testing CenterInventors: Po-Hsu Lin, Chung-Che Huang
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Publication number: 20190199121Abstract: A method for distributing power using multiple power sources is performed by a control device electrically connected to multiple rechargeable power units and a load. The control device creates an output power reference table according to multiple power setting values, output power ranges and battery efficiencies of the multiple rechargeable power units. The output power reference table includes the power setting values and power distribution information corresponding to the power setting values. When receiving a consumed power value of the load, the control device selects corresponding power setting value and power distribution information in the output power reference table and controls the multiple rechargeable power units to simultaneously output power to the load according to the power distribution information. By referring to the output power values of all the rechargeable power units and allocating power outputted from all the rechargeable power units, power utilization efficiency can be enhanced.Type: ApplicationFiled: December 26, 2017Publication date: June 27, 2019Inventors: Po-Hsu Lin, Chung-Che Huang
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Patent number: 10110022Abstract: A battery charging apparatus includes a charging module and a control module. The control module obtains a DIR (dynamic internal resistance) of a battery cell group based on a voltage and a current of the battery cell group, and generates a control signal based on the voltage and the DIR of the battery cell group. The charging module alternates between outputting and not outputting a charge current/voltage to charge the battery cell group based on the control signal.Type: GrantFiled: December 2, 2015Date of Patent: October 23, 2018Assignee: Automotive Research & Testing CenterInventors: Bo-Han Hwang, Deng-He Lin, Chung-Che Huang
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Publication number: 20180188329Abstract: A device for estimating a state-of-health (SOH) of a battery module controls a battery current to have a predetermined current value for a testing period such that a battery voltage decreases during the testing period, corrects a voltage variation value of the battery module during the testing period according to a temperature value of the battery module, and estimates the SOH of the battery module according to the corrected voltage variation value, a current variation value of the battery module during the testing period, and a rated capacity of the battery module.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Chung-Che HUANG, Po-Hsu LIN, Zhi-Rong WANG
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Publication number: 20170163050Abstract: A battery charging apparatus includes a charging module and a control module. The control module obtains a DIR (dynamic internal resistance) of a battery cell group based on a voltage and a current of the battery cell group, and generates a control signal based on the voltage and the DIR of the battery cell group. The charging module alternates between outputting and not outputting a charge current/voltage to charge the battery cell group based on the control signal.Type: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Inventors: Bo-Han Hwang, Deng-He Lin, Chung-Che Huang
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Patent number: 9613826Abstract: A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H2/N2 plasma treatment process is performed to reduce the main conductive material.Type: GrantFiled: July 29, 2015Date of Patent: April 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Chi Tai, Chun-Ju Tao, Chung-Che Huang
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Publication number: 20170032975Abstract: A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H2/N2 plasma treatment process is performed to reduce the main conductive material.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Inventors: Cheng-Chi Tai, Chun-Ju Tao, Chung-Che Huang
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Patent number: 9412851Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.Type: GrantFiled: December 23, 2013Date of Patent: August 9, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
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Publication number: 20150179748Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chang, Ping-Chia Shih, Chi-Cheng Huang, Kuo-Lung Li, Kun-I Chou, Chung-Che Huang, Chia-Cheng Hsu, Mu-Jia Liu
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Patent number: 9040423Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.Type: GrantFiled: July 17, 2013Date of Patent: May 26, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
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Publication number: 20150024598Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
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Patent number: 8034690Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.Type: GrantFiled: January 29, 2010Date of Patent: October 11, 2011Assignee: United Microelectronics Corp.Inventors: Ping-Chia Shih, Yu-Cheng Wang, Chun-Sung Huang, Yuan-Cheng Yang, Chung-Che Huang, Chin-Fu Lin
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Publication number: 20110189859Abstract: An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Inventors: Ping-Chia Shih, Yu-Cheng Wang, Chun-Sung Huang, Yuan-Cheng Yang, Chung-Che Huang, Chin-Fu Lin
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Publication number: 20070074541Abstract: The invention relates to synthesis of germanium sulphide glasses and optical devices formed therefrom. In a chemical vapour deposition process, germanium tetrachloride is reacted with hydrogen sulphide at temperatures in the range 450-700° C. to form germanium sulphide. Lower temperatures within this range of 450-550° C. directly produce a glass, whereas higher temperatures within the range of 600-700° C. produce a crystalline powder which can then be reduced to a glass by subsequent melting and annealing. The reaction is preferably carried out at atmospheric pressure or slightly higher. Thin films and bulk glasses suitable for optical waveguides can be formed directly in one processing step as can powders and microspheres. The materials synthesised are of a high purity with low oxide impurities and only trace levels of transition metal ions.Type: ApplicationFiled: October 8, 2004Publication date: April 5, 2007Applicant: University of SouthamptonInventors: John Badding, Daniel Hewak, Chung-Che Huang