Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.

Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.

Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.

Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N?M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N?M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N?M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N?M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract: A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

Abstract: A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.