Patents by Inventor Chung-Chi Ko

Chung-Chi Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160086865
    Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 24, 2016
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 9236294
    Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Po-Cheng Shih, Chih-Hung Sun, Kuang-Yuan Hsu, Joung-Wei Liou, Tze-Liang Lee
  • Patent number: 9196551
    Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 9153538
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface of the via portion of each conductive feature. The barrier layer includes a dielectric layer. A first insulating material layer is disposed beneath a portion of the conductive line portion of each conductive feature. A second insulating material layer is disposed between the conductive features. A third insulating material layer is disposed beneath the first insulating material layer and the second insulating material layer. A lower portion of the via portion of each of the conductive features is formed within the third insulating material layer.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Pei-Wen Huang, Chih-Hao Chen, Kuang-Yuan Hsu, Tze-Liang Lee
  • Patent number: 9136226
    Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Chung-Chi Ko
  • Patent number: 9130017
    Abstract: A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin
  • Patent number: 9093265
    Abstract: One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Hui-Chun Yang, Chung-Chi Ko, Kuang-Yuan Hsu
  • Patent number: 9087877
    Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Ting-Yu Shen, Keng-Chu Lin, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
  • Publication number: 20150200133
    Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng CHOU, Chung-Chi KO, Po-Cheng SHIH, Chih-Hung SUN, Kuang-Yuan HSU, Joung-Wei LIOU, Tze-Liang LEE
  • Publication number: 20150201501
    Abstract: A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Chih-Chien Chi, Chung-Chi Ko, Mei-Ling Chen, Hung-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Publication number: 20150194343
    Abstract: A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien CHI, Chung-Chi KO, Mei-Ling CHEN, Hung-Yi HUANG, Szu-Ping TUNG, Ching-Hua HSIEH
  • Publication number: 20150187697
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 2, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
  • Publication number: 20150104953
    Abstract: One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Hui-Chun Yang, Chung-Chi Ko, Kuang-Yuan Hsu
  • Patent number: 9004914
    Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia Cheng Chou, Keng-Chu Lin, Joung-Wei Liou, Shwang-Ming Jeng, Mei-Ling Chen
  • Publication number: 20150091172
    Abstract: The present disclosure relates to a method of forming pore sealing layer for porous low-k dielectric interconnects. The method is performed by removing hard mask layer before pore sealing and/or applying pore sealing layer before etching etch stop layer (ESL). These methods at least have advantages that aspect ratio is improved, line distortion introduced by the hard mask layer is avoided, and critical dimension is less affected by pore sealing layer.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chi Ko, Pei-Wen Huang, Chun-Yi Lee, Kuang-Yuan Hsu, Tze-Liang Lee
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Publication number: 20150054170
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes conductive features disposed over a workpiece, each conductive feature including a conductive line portion and a via portion. A barrier layer is disposed on sidewalls of each conductive feature and on a bottom surface of the via portion of each conductive feature. The barrier layer includes a dielectric layer. A first insulating material layer is disposed beneath a portion of the conductive line portion of each conductive feature. A second insulating material layer is disposed between the conductive features. A third insulating material layer is disposed beneath the first insulating material layer and the second insulating material layer. A lower portion of the via portion of each of the conductive features is formed within the third insulating material layer.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Pei-Wen Huang, Chih-Hao Chen, Kuang-Yuan Hsu, Tze-Liang Lee
  • Patent number: 8940643
    Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chih-Hao Chen, Keng-Chu Lin
  • Patent number: 8846528
    Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin
  • Patent number: 8629056
    Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao, Chen-Hua Yu