Abstract: A method of fabricating a semiconductor device includes providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: A silicon carbide substrate includes an N-type silicon carbide substrate having a first surface and a second surface opposite to the first surface. The N-type silicon carbide substrate includes a semi-insulating silicon carbide region and an N-type silicon carbide region. The semi-insulating silicon carbide region extends inward from the first surface into the N-type silicon carbide substrate to a depth. The semi-insulating silicon carbide region includes nitrogen and a first dopant. The first dopant includes at least one of group VB elements, group VIIA elements, argon and silicon. The N-type silicon carbide region is adjacent to the semi-insulating silicon carbide region and includes nitrogen element.

Abstract: A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

Abstract: An unmanned flying spray system includes a flying device, an air valve, and a spraying device. The flying device is provided with a controller including a control module and a power supply module electrically connected to the control module for supplying power to the flying device. The air valve is disposed on the flying device and connected with a gas cylinder for outputting a gas power. The spraying device includes a pesticide container, an electromagnetic control valve electrically connected with the control module, and a nozzle. The pesticide container has a diverting member connected with the air valve, the pesticide container, and the nozzle. The electromagnetic valve is disposed between the diverting member and the nozzle. The unmanned flying spray system sprays a liquid by use of gas power, so as to significantly reduce the overall weight and improve the stability of flying.

Abstract: A coaxial probe card device includes a substrate, a plurality of probe holders, and a plurality of probes. The substrate has a through hole. The plurality of probe holders is disposed on the substrate and is configured in a radial manner surrounding the through hole by using the through hole of the substrate as a center. Each probe holder has a probe slot, and the probe slot is inclined with respect to a surface of the substrate and extends towards the through hole of the substrate. The probes are individually disposed in the probe slots of the probe holders.

Abstract: An encryption method adopts an encryption principle based on sequential logic and involves performing three dimensional computation on a plaintext data unit having undergone non-linear transition through a dynamic child transition box, system keys, and dynamic feedback keys together to generate dynamic keys. After undergoing non-linear transition through different dynamic child transition boxes respectively, the dynamic keys undergo the three dimensional computation together with the system keys to generate a ciphertext data unit. Content values of the dynamic feedback keys and dynamic child transition box operating under a feedback control mechanism vary with each instance of feedback, and thus the dynamic keys and the ciphertext data are difficult to crack but effective in resisting violent attacks.

Abstract: An independently controllable transmission mechanism with an identity-ratio series type includes a first planetary gear train and a second planetary gear train mechanically connected therewith. The transmission mechanism has a power output end, a transmission control end, a power input end and a free transmission end. The power output end and the transmission control end are provided on the first planetary gear train and the second planetary gear train, respectively. The power input end is provided on the first planetary gear train or the second planetary gear train while the free transmission end is provided on the second planetary gear train or the first planetary gear train. The transmission control end is operated to freely shift the free transmission end as a power input end or a power output end.

Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.