Abstract: A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Abstract: The invention provides a recycling method of polyester cotton blended fabrics, which includes the following steps. First, the polyester cotton blend fabric is cuts into fragments. Afterwards, the fragments are placed in a reactor, a mixed aqueous solution of an acidic compound and a metal catalyst is added, a temperature is raised to 110° C. to 160° C., and a reaction is carried out for 1 to 6 hours to cleave the cotton fibers. Next, filter and separate to obtain cotton powders and a polyester fiber.

Abstract: A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

Abstract: Imaging systems and techniques are described. In some examples, an imaging system generates a segmentation map of an image by processing image data associated with the image using a segmentation mapper. Different object types in the image are categorized into different regions in the segmentation map. The imaging system generates an augmented segmentation map by processing at least the segmentation map using a segmentation map error correction engine. The imaging system generates processed image data by processing the image using the augmented segmentation map.

Abstract: Methods, systems, and apparatuses for image segmentation are provided. For example, a computing device may obtain an image, and may apply a process to the image to generate input image feature data and input image segmentation data. Further, the computing device may obtain reference image feature data and reference image classification data for a plurality of reference images. The computing device may generate reference image segmentation data based on the reference image feature data, the reference image classification data, and the input image feature data. The computing device may further blend the input image segmentation data and the reference image segmentation data to generate blended image segmentation data. The computing device may store the blended image segmentation data within a data repository. In some examples, the computing device provides the blended image segmentation data for display.

Abstract: A vehicle lamp is mounted on a vehicle body in which a front-rear direction of the vehicle body is a first direction. The vehicle lamp comprises a light emitting unit and an optical unit. The light emitting unit includes at least one light emitting member. The optical unit includes at least one lens having a light incident portion, a reflective portion, and a light output portion. The light incident portion is disposed corresponding to the light emitting member. The light output portion is disposed along a second direction at a slant angle relative to the first direction. The reflective portion includes a plurality of reflective faces arranged in an array. The light emitting member emits light rays which pass through the light incident portion into the lens. The reflective portion reflects the light rays to the light output portion to thereby output the light rays.

Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

Abstract: A method includes forming a silicon layer on a wafer, forming an oxide layer in contact with the silicon layer, and, after the oxide layer is formed, annealing the wafer in an environment comprising ammonia (NH3) to form a dielectric barrier layer between, and in contact with, the silicon layer and the oxide layer. The dielectric barrier layer comprises silicon and nitrogen.

Abstract: Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

Abstract: A method of forming an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

Abstract: The present disclosure is directed to circuits and a method for mitigating effects of power supply variations on a driver circuit. For example, the circuit can include a first transistor device with a first source/drain (S/D) terminal and a second S/D terminal. The circuit can also include a second transistor device with a third S/D terminal and a fourth S/D terminal. The driver circuit can further include a resistor device electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals. The resistor device can mitigate variations in a high-level output voltage of the driver circuit due to power supply variations.

Abstract: A method for degumming and decolorizing polyester fabrics is provided. The method includes the following steps. A first polyester fabric attached with a dye and a gum-film or treatment agent is provided. The gum-film or treatment agent in the first polyester fabric is stripped through a combined formulation of an alkaline aqueous solution and a catalyst to obtain a second polyester fabric. Then, the second polyester fabric is decolorized by a combination of a chemical reduction method and a chemical oxidation method to obtain a third polyester fabric.

Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

Abstract: A contacting member of a contact probe for a probe system for performing a functionality test to a DUT includes a body, a contact tip, and a tip transition section between the body and the contact tip. A bottom side of the contacting member, which faces toward the DUT when testing the DUT, includes a lower surface at the body, a tip bottom surface at the contact tip, and a tip transition surface at the tip transition section. A contact end of the contact tip for contacting the DUT is located on a front side of the tip bottom surface. A rear side of the tip bottom surface and the lower surface have a height difference therebetween. The tip transition surface gradually changes in height from the lower surface to the rear side of the tip bottom surface. The contacting member has high precision and structural strength.

Abstract: Systems and techniques are described herein for determining changes in distance. For instance, an apparatus for determining changes in distance is provided. The apparatus may include an electromagnetic (EM)-radiation emitter configured to emit EM radiation toward an environment; a detector configured to receive reflected EM radiation from the environment; phase-calculation circuitry configured to calculate a phase-difference value indicative of a difference between a phase of the emitted EM radiation and a phase of the reflected EM radiation; and differencing circuitry configured to trigger an event responsive to a difference between a current phase-difference value and a prior phase-difference value exceeding a threshold.

Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.

Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.

Abstract: An integrated circuit structure includes a bulk semiconductor region, a first semiconductor strip over and connected to the bulk semiconductor region, and a dielectric layer including silicon oxide therein. Carbon atoms are doped in the silicon oxide. The dielectric layer includes a horizontal portion over and contacting a top surface of the bulk semiconductor region, and a vertical portion connected to an end of the horizontal portion. The vertical portion contacts a sidewall of a lower portion of the first semiconductor strip. A top portion of the first semiconductor strip protrudes higher than a top surface of the vertical portion to form a semiconductor fin. The horizontal portion and the vertical portion have a same thickness. A gate stack extends on a sidewall and a top surface of the semiconductor fin.