Patents by Inventor Chung-Chi Wang
Chung-Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961866Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.Type: GrantFiled: October 27, 2020Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiao-Chi Wang, Chia-Ping Lai, Chung-Chuan Tseng
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Publication number: 20240120304Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.Type: ApplicationFiled: November 24, 2022Publication date: April 11, 2024Applicant: Innolux CorporationInventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
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Publication number: 20220222194Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Neelam CHANDWANI, Shridhar BENDI, Rajesh VIVEKANANDHAM, Rahul PAL, Eric J. DAHLEN, Antonio J. HASBUN MARIN, Chung-Chi WANG, Qian LI, Hosein NIKOPOUR, Sravanthi KOTA VENKATA, Rajesh POORNACHANDRAN, Udayan MUKHERJEE
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Publication number: 20210294772Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Amit Kumar Srivastava, Divya Gupta, Michael Karas, James Mitchell, Malay Trivedi, Chung-Chi Wang
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Patent number: 10193826Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.Type: GrantFiled: July 15, 2015Date of Patent: January 29, 2019Assignee: INTEL CORPORATIONInventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, Jr., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
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Publication number: 20170019350Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.Type: ApplicationFiled: July 15, 2015Publication date: January 19, 2017Inventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, JR., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
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Publication number: 20150044432Abstract: The present invention discloses a touch panel structure and a method for forming the same. A touch panel structure according to the present invention comprises a substrate, a first color layer, a second color layer, and an indium tin oxide (ITO) conductive layer. The first color layer is disposed on a surface of the substrate. The second color layer is disposed on a surface of the first color layer which is opposite to the substrate, and a portion of the second color layer extends further to be in contact with the substrate. The ITO conductive layer is disposed on a surface of the second color layer which is opposite to the first color layer and also disposed on the surface of the substrate. With the touch panel structure of the present invention, the conductive layer will not break easily, and the yield rates for touch panels will be improved.Type: ApplicationFiled: June 5, 2014Publication date: February 12, 2015Inventors: CHUNG-CHI WANG, KAO-HUI SU
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Publication number: 20150029415Abstract: The present invention discloses a touch panel structure, a method for forming the same and a touch device having the same. A touch panel structure of the present invention comprises a substrate, a color layer, an inorganic layer, and a photoresist layer. The color layer is disposed on a surface of the substrate. The inorganic layer is disposed on a surface of the color layer which is opposite to the substrate. The photoresist layer is disposed on a surface of the inorganic layer which is opposite to the substrate, wherein the color layer and the photoresist layer have different surface tensions. For electronic products that rely on the Colorful OGS (One Glass Solution) technology, by providing an inorganic layer between the color layer and the photoresist layer, problems related to different surface tensions when the layers are stacked during the manufacturing process of a touch panel can be solved.Type: ApplicationFiled: April 21, 2014Publication date: January 29, 2015Applicant: CANDO CORPORATIONInventors: CHUNG-CHI WANG, YUN-WEN CHEN
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Publication number: 20150009423Abstract: The present invention discloses a touch panel structure, a method for forming the same and a touch device comprising the same. A touch panel structure of the present invention comprises a substrate, a color layer, and a shielding layer. The shielding layer is disposed on a surface of the color layer which is opposite to the substrate. The shielding layer has at least one hollow area, and the color layer has a transmittance of more than 1%. With the present invention, the logo and function key icons and their surrounding area on a touch device share a same color layer of the same material. Therefore, the visual color difference perceived by the user is eliminated.Type: ApplicationFiled: March 31, 2014Publication date: January 8, 2015Applicant: CANDO CORPORATIONInventors: CHUNG-CHI WANG, YUN-WEN CHEN, YAO-HUI HUANG
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Patent number: 8144318Abstract: The present invention is directed to a method of calibrating sensitivity gain. In a preview mode, an imaging device is calibrated by a standard light source, therefore obtaining standard sensitivity gain of the preview mode. In a capture mode, the imaging device is calibrated by the standard light source, therefore obtaining standard sensitivity gain of the capture mode. A gain ratio of the standard sensitivity gain of the capture mode to the standard sensitivity gain of the preview mode is determined, and is then used to deduce the exposure parameters of the capture mode according to the exposure parameters of the preview mode.Type: GrantFiled: April 22, 2010Date of Patent: March 27, 2012Assignee: Ability Enterprise Co., Ltd.Inventors: Chung-Chi Wang, Yi-Jian Lee
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Publication number: 20110179311Abstract: In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.Type: ApplicationFiled: December 17, 2010Publication date: July 21, 2011Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Sarathy Jayakumar, Chung-Chi Wang
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Publication number: 20110161592Abstract: In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Chung-Chi Wang
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Publication number: 20110157583Abstract: The present invention is directed to a method of calibrating sensitivity gain. In a preview mode, an imaging device is calibrated by a standard light source, therefore obtaining standard sensitivity gain of the preview mode. In a capture mode, the imaging device is calibrated by the standard light source, therefore obtaining standard sensitivity gain of the capture mode. A gain ratio of the standard sensitivity gain of the capture mode to the standard sensitivity gain of the preview mode is determined, and is then used to deduce the exposure parameters of the capture mode according to the exposure parameters of the preview mode.Type: ApplicationFiled: April 22, 2010Publication date: June 30, 2011Applicant: ABILITY ENTERPRISE CO., LTD.Inventors: CHUNG-CHI WANG, YI-JIAN LEE
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Patent number: 7600080Abstract: In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.Type: GrantFiled: September 22, 2006Date of Patent: October 6, 2009Assignee: Intel CorporationInventors: Binata Bhattacharyya, Chandra P. Joshi, Chung-Chi Wang, Liang Yin, Vivek Garg, Phanindra K. Mannava
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Patent number: 6885378Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.Type: GrantFiled: September 28, 2000Date of Patent: April 26, 2005Assignee: Intel CorporationInventors: Hsin-Chu Tsai, Subramaniam Maiyuran, Chung-Chi Wang
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Patent number: D879200Type: GrantFiled: August 20, 2018Date of Patent: March 24, 2020Assignee: ROYAL JET ENTERPRISE CORP.Inventor: Chung-Chi Wang