Patents by Inventor Chung-Chieh TING

Chung-Chieh TING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220392799
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 8, 2022
    Inventors: Chung-Lei CHEN, Cheng-Hsin CHEN, Chung Chieh TING, Che-Yi LIN, Clark LEE
  • Patent number: 11443976
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Cheng-Hsin Chen, Chung Chieh Ting, Che-Yi Lin, Clark Lee
  • Publication number: 20220122880
    Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Chung-Lei CHEN, Cheng-Hsin CHEN, Chung Chieh TING, Che-Yi LIN, Clark LEE
  • Publication number: 20210384044
    Abstract: A method of fabricating a semiconductor device is provided, including providing a base substrate and a die stacking unit mounted on the base substrate. Conductive joints are connected between two adjacent dies of the die stacking unit. The method further includes providing dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. In addition, the method includes filling the gaps between the base substrate, all dies of the die stacking unit, the conductive joints, the dummy micro bumps, and the dummy pads with an underfill material by capillary attraction.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU
  • Patent number: 11101145
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Chen-Hsuan Tsai, Chung-Chieh Ting, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20200058519
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.
    Type: Application
    Filed: November 1, 2018
    Publication date: February 20, 2020
    Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU