Patents by Inventor Chung-Chien Lin

Chung-Chien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062696
    Abstract: A secondary-side controller applied to a flyback power converter prevents a secondary side of the flyback power converter from conducting incorrectly. The secondary-side controller includes a first comparison circuit, a second comparison circuit, and a gate control signal generation circuit. The first comparison circuit generates a first comparison signal according to a drain voltage of a synchronous switch of the secondary side of the flyback power converter and a first parameter. The second comparison circuit generates a ready signal according to the first comparison signal and a resistance of an external resistor. The gate control signal generation circuit generates a gate control signal to the synchronous switch according the ready signal and the drain voltage, and the synchronous switch is turned on according to the gate control signal.
    Type: Application
    Filed: April 24, 2024
    Publication date: February 20, 2025
    Applicant: Leadtrend Technology Corp.
    Inventors: Jun-Hao Huang, Tsung-Chien Wu, Chung-Wei Lin, Ming-Chang Tsou
  • Publication number: 20250030351
    Abstract: Disclosed is the source active region.
    Type: Application
    Filed: April 16, 2024
    Publication date: January 23, 2025
    Inventors: Tsung-Chien WU, Jun-Hao HUANG, Chung-Wei LIN, Ming-Chang TSOU
  • Publication number: 20170198491
    Abstract: A calculus structure has a plurality of unit components and a plurality of joint components is provided. The unit components and the joint components are adapted to form a target structure. Each end of each of the joint components has an embedding construction or an embedded construction. Each of the unit components and the joint components has a bore therein for communication with each other. The bore is adapted to allow a cascading part to pass therethrough so that the unit components and the joint components are cascaded together by the cascading part, and the unit components and the joint components are movable relative to the cascading part so that the unit components and the joint components abut against each other in a cascading order to form the target structure.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventor: Chung-Chien LIN
  • Publication number: 20160097965
    Abstract: A stand style rear lens cap for use in a detachable lens of a camera is disclosed. The stand style rear lens cap includes a stand body having an upper end including a horizontal plane, and the horizontal plane having a central opening adapted for a rear-end projection of the detachable lens to pass therethrough, wherein a first diameter of the central opening is smaller than a second diameter of a lens body distal end of the detachable lens, a first depth of the central opening is larger than or equal to a height of the rear-end projection of the detachable lens, and an inner wall of the central opening is provided with a component that correspondingly engages with the rear-end projection of the detachable lens.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 7, 2016
    Inventor: Chung-Chien LIN
  • Patent number: 7613952
    Abstract: A method for facilitating basic input and output system (BIOS) testing is provided. In the method, a BIOS program code to be tested is loaded into a memory unit by a BIOS debugging card to execute a boot operation testing. The method of BIOS testing utilizes an uninterruptible power supply memory disposed on the motherboard. The uninterruptible power supply memory is powered with a battery, thus it can store the data of a command in executing during shutdown. By using this characteristic of the uninterruptible power supply memory, the tester can still obtain the debugging code last stored during the previous boot from the uninterruptible power supply memory when rebooting, thus preventing the debugging code generated in the BIOS debugging flow from disappearing due to the abnormal shutdown and resulting in the failure to get the source of the problem for the tester, increasing the efficiency of debugging.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 3, 2009
    Assignee: Inventec Corporation
    Inventors: Chien-Hsing Ko, Chia-I Hsiao, Chung-Chien Lin
  • Publication number: 20080163001
    Abstract: A method for facilitating basic input and output system (BIOS) testing is provided. In the method, a BIOS program code to be tested is loaded into a memory unit by a BIOS debugging card to execute a boot operation testing. The method of BIOS testing utilizes an uninterruptible power supply memory disposed on the motherboard. The uninterruptible power supply memory is powered with a battery, thus it can store the data of a command in executing during shutdown. By using this characteristic of the uninterruptible power supply memory, the tester can still obtain the debugging code last stored during the previous boot from the uninterruptible power supply memory when rebooting, thus preventing the debugging code generated in the BIOS debugging flow from disappearing due to the abnormal shutdown and resulting in the failure to get the source of the problem for the tester, increasing the efficiency of debugging.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Applicant: Inventec Corporation
    Inventors: Chien-Hsing Ko, Chia-I Hsiao, Chung-Chien Lin