Patents by Inventor Chung-Chih Chen
Chung-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145571Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.Type: ApplicationFiled: January 5, 2023Publication date: May 2, 2024Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11967570Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.Type: GrantFiled: March 4, 2022Date of Patent: April 23, 2024Assignee: MediaTek Inc.Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
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Patent number: 11968856Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.Type: GrantFiled: October 4, 2021Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Po-Jui Chen, Hoang Yan Lin, Guo-Dong Su, Wei-Kai Lee, Chi-Jui Chang, Wan-Yu Lin, Byung Sung Kwak, Robert Jan Visser
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Publication number: 20240128324Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.Type: ApplicationFiled: November 21, 2022Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240116707Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Chung-Yu Liu
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Patent number: 11956994Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.Type: GrantFiled: August 10, 2021Date of Patent: April 9, 2024Assignee: Applied Materials, Inc.Inventors: Chung-Chih Wu, Hoang Yan Lin, Guo-Dong Su, Zih-Rou Cyue, Li-Yu Yu, Wei-Kai Lee, Guan-Yu Chen, Chung-Chia Chen, Wan-Yu Lin, Gang Yu, Byung-Sung Kwak, Robert Jan Visser, Chi-Jui Chang
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Publication number: 20240100352Abstract: A phototherapy device includes a base, at least one light conversion device and a light source module. The base has an installation slot. The light conversion device is detachably arranged in the installation slot. Each light conversion device includes a plurality of light conversion patterns. The light source module is arranged on a side of the base and configured to provide an excitation beam to the light conversion patterns, so that each of the light conversion patterns emits a converted beam. In this way, the light conversion device of the phototherapy device can be replaced according to the user's needs.Type: ApplicationFiled: September 19, 2023Publication date: March 28, 2024Inventors: CHUNG-JEN OU, YU-MIN CHEN, MING-WEI TSAI, CHIEN-CHIH CHEN
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Publication number: 20240099005Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending bet ween the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Sheng-Chih Lai, Chung-Te Lin, Yung-Yu Chen
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Patent number: 11699673Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.Type: GrantFiled: May 17, 2021Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
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Publication number: 20210272919Abstract: A semiconductor package is provided, including a package component and a number of conductive features. The package component has a non-planar surface. The conductive features are formed on the non-planar surface of the package component. The conductive features include a first conductive feature and a second conductive feature respectively arranged in a first position and a second position of the non-planar surface. The height of the first position is less than the height of the second position, and the size of the first conductive feature is smaller than the size of the second conductive feature.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
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Patent number: 11011487Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.Type: GrantFiled: June 22, 2020Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
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Patent number: 10872831Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.Type: GrantFiled: April 22, 2019Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Shin Han, Yen-Miao Lin, Chung-Chih Chen, Hsien-Liang Meng
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Publication number: 20200321297Abstract: A semiconductor package is provided, including a package component and a number of conductive connectors. The package component has a number of conductive features on a surface of the package component. The conductive connectors are formed on the conductive features of the package component. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
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Patent number: 10700030Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.Type: GrantFiled: January 28, 2019Date of Patent: June 30, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Lin, Chien-Kuo Chang, Tzu-Kai Lan, Chung-Chih Chen, Jr-Lin Hsu
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Patent number: 10601677Abstract: The invention provides a method for a dynamical virtual a private network, which is suitable for a main device in a dynamic virtual private network. The method comprises: (a) before the main device establishes a tunneling connection, acquiring a request for adding a sub-device to a whitelist directly or through a third-party cloud service and sending an acceptance message or a rejection message to the sub-device accordingly thereto; (b) acquiring a request for connecting with the sub-device directly or through the third-party cloud service, and determining whether the tunneling connection with the sub-device is established or not accordingly thereto or sending a rejection message to the sub-device; (c) after the tunneling connection is established between the main device and the sub-device, receiving a connection code sent from the sub-device through the tunneling connection, and determining whether the connection code sent from the sub-device is correct or not.Type: GrantFiled: July 25, 2018Date of Patent: March 24, 2020Assignee: INFORICH ELECTRONICS CORP.Inventors: Chung-Chih Chen, Shi-Ming Zhao
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Publication number: 20200058611Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.Type: ApplicationFiled: January 28, 2019Publication date: February 20, 2020Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
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Publication number: 20200036600Abstract: The invention provides a method for a dynamical virtual a private network, which is suitable for a main device in a dynamic virtual private network. The method comprises: (a) before the main device establishes a tunneling connection, acquiring a request for adding a sub-device to a whitelist directly or through a third-party cloud service and sending an acceptance message or a rejection message to the sub-device accordingly thereto; (b) acquiring a request for connecting with the sub-device directly or through the third-party cloud service, and determining whether the tunneling connection with the sub-device is established or not accordingly thereto or sending a rejection message to the sub-device; (c) after the tunneling connection is established between the main device and the sub-device, receiving a connection code sent from the sub-device through the tunneling connection, and determining whether the connection code sent from the sub-device is correct or not.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Chung-Chih Chen, Shi-Ming Zhao
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Publication number: 20190252277Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Shin HAN, Yen-Miao LIN, Chung-Chih CHEN, Hsien-Liang MENG