Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to capture images. A method of processing image data includes determining a first region of interest (ROI) in an image. The first ROI is associated with a first object. The method can include determining one or more image characteristics of the first ROI. The method can further include determining whether to perform an upsampling process on image data in the first ROI based on the one or more image characteristics of the first ROI.

Abstract: An oven includes an oven body, a heating element, a frame, and an oven door. The oven body has an inner space inside and includes a front plate, wherein the front plate has an entrance that communicates with the inner space. The heating element is adapted to heat the inner space. The frame is engaged with the oven body and has an abutted portion. The oven door is pivotally connected to the oven body and is located at the entrance. The oven door can pivot to a closed position to close the entrance and can pivot downward to an open position from the closed position to open the entrance. When the oven door is located at the open position, the second surface abuts against the abutted portion of the frame, thereby forming a platform outside the entrance for placing objects.

Abstract: A photo mask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterning region of a device region. The first assist feature are in the patterning region and adjacent to the device features. The first assist feature is for correcting an optical proximity effect in a photolithography process. The second assist feature is in a non-patterning region of the device region. The second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.

Abstract: A heterojunction bipolar transistor structure is provided, including a substrate and a multi-layer structure formed on the substrate. The multi-layer structure includes a current clamping layer, and the current clamping layer can be disposed in a collector layer, disposed in a sub-collector layer, or interposed between a collector layer and a sub-collector layer. An electron affinity of the current clamping layer is less than an electron affinity of an epitaxial layer formed on the current clamping layer.

Abstract: The present invention is a semiconductor device having a defect blocking region. The semiconductor device includes a substrate, a defect source region, a semiconductor layer and a defect blocking region. The defect source region is on the substrate, wherein the defect source region is a metamorphic buffer layer or a buffer layer, the semiconductor layer over the defect source region, wherein a lattice constant of the semiconductor layer is different from a lattice constant of the substrate. The defect blocking region is disposed on the substrate and below the semiconductor layer, wherein the defect blocking region includes a superlattice structure, wherein at least one of two adjacent layers of the superlattice structure has strain relative to the semiconductor layer, or a lattice constant of the superlattice structure is close to or equal to the lattice constant of the semiconductor layer.

Abstract: A battery balancing system includes a voltage sensing unit, a characteristic voltage selector and a control unit. The voltage sensing unit senses a battery voltage of each of the batteries connected in series in a battery group and generates corresponding battery voltage sensing signals. The characteristic voltage selector generates a characteristic voltage according to the battery voltage sensing signals. The control unit compares the characteristic voltage with a threshold voltage in a balance operation mode, to adaptively adjust the threshold voltage, and compares the battery voltage sensing signal with the adjusted threshold voltage to generate a battery balancing command, thereby executing a charge removal balancing command or a charge supplying balancing command on the corresponding battery, or thereby cease executing the charge removal balancing command or cease executing the charge supplying balancing command on the corresponding battery.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A semiconductor laser diode includes a substrate; a lower epitaxial region located on the substrate, wherein the lower epitaxial region includes a lower DBR layer; an active region located on the lower epitaxial region; and an upper epitaxial region located on the substrate, wherein the upper epitaxial region includes a lower DBR layer; wherein the lower DBR layer includes a P-type lower DBR region and the upper DBR layer includes an N-type upper DBR region.

Abstract: A method for blood plasma protein activity preservation is provided. The method comprises the steps of mixing blood plasma with two or more protectants selected from the group consisting of triglyceride, glycerol, propylene glycol, alanine, serine, glycine, alginate, and sucrose to obtain a mixture; and lyophilizing the mixture.

Abstract: Provided is a semiconductor laser diode, including a GaAs/In P substrate and a multi-layer structure on the GaAs/InP substrate. The multi-layer structure includes a lower epitaxial region, an active region and an upper epitaxial region. The active region comprises a first active layer, an epitaxial region and a second active layer, the epitaxial region is disposed between the first active layer and the second active layer, the first active layer comprises one or more quantum well structures or one or more quantum dot structures, and the second active layer comprises one or more quantum well structures or one or more quantum dot structures.

Abstract: A semiconductor laser epitaxial structure includes a horizontal cavity configured to generate an optical field distribution, a grating layer located within the optical field distribution, a first semiconductor optical amplifier disposed between a light-emitting surface of the semiconductor laser epitaxial structure and the horizontal cavity, and a first tunnel junction layer disposed between the horizontal cavity and the first semiconductor optical amplifier. The grating layer is configured to convert a horizontal light to a vertical light. The semiconductor laser epitaxial structure does not require alignment, the yield rate of manufacturing the semiconductor laser is increased, and the manufacturing cost and manufacturing processes can be reduced.

Abstract: A pressure regulating device includes a pressure stabilizer including a valve body, a pressure regulating assembly, and a switching assembly. The valve body has an inlet portion, a decompression chamber communicating with the inlet portion, and an outlet portion. The inlet portion has an inlet port for connecting to an outlet opening of a portable gas tank. The outlet portion communicates with the decompression chamber and has an outlet port. The pressure regulating assembly is disposed in the decompression chamber. The pressure regulating assembly regulates the pressure of gas outputted by the portable gas tank to form an output gas with a predetermined pressure. The switching assembly is disposed on the outlet portion and is located between the decompression chamber and the outlet port and is manipulatable to block or open the output gas, thereby regulating the pressure of the output gas outputted by the portable gas tank.

Abstract: Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.

Abstract: A disinfection system includes an ultraviolet disinfecting light, a controlling device, and an ultraviolet detecting device. The ultraviolet disinfecting light can be turned on or off under control. The controlling device controls the ultraviolet disinfecting light to be turned on or off. The ultraviolet detecting device is signally connected to the controlling device and is for detecting an intensity of the ultraviolet rays emitted by the ultraviolet disinfecting light. The controlling device controls the ultraviolet disinfecting light to increase an ultraviolet radiation dose of the ultraviolet rays emitted by the ultraviolet disinfecting light after the ultraviolet disinfecting light is turned on and the intensity of the ultraviolet rays is less than a predetermined intensity. An elevator equipment includes a car, a lift control device, and the disinfection system. In this way, the space can be disinfected with the ultraviolet rays to avoid insufficient disinfection effect.

Abstract: A vertical cavity surface-emitting laser epitaxial structure having a current spreading layer is disclosed. The vertical cavity surface-emitting laser epitaxial structure includes a substrate, a first epitaxial region on the substrate, an active region on the first epitaxial region, and a current spreading layer disposed in the first epitaxial region. The current spreading layer includes an N-type dopant, and the N-type dopant is selected from a group consisting of Si, Se, and the combination thereof. The current spreading layer does not directly contact the active region.

Abstract: Provided is a heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a bandgap graded layer. A quasi-electric field generated by the bandgap graded layer will enable electrons in the bandgap graded layer to be accelerated. The bandgap graded layer includes a semiconductor material in which an electron velocity peaks at a certain quasi-electric field strength when an quasi-electric field strength is varied, wherein the certain quasi-electric field strength is referred to as a peak electric field strength. The strength of the quasi-electric field is more than 2 times the peak electric field strength.