Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

Abstract: Methods, apparatus, and systems for multi-resolution processing for video classification. A plurality of video frames of a video are obtained and a resolution for classifying each video frame of the plurality of video frames is determined by analyzing each video frame using a policy network. Based on the determined resolution, each video frame having a determined resolution is rescaled and each rescaled video frame is routed to a classifier of a backbone network that corresponds to the determined resolution. Each rescaled video frame is classified using the corresponding classifier of the backbone network to obtain a plurality of classifications and the classifications are averaged to determine an action classification of the video.

Abstract: Some embodiments relate to a thin film transistor comprising an active layer over a substrate. An insulator is stacked with the active layer. A gate electrode structure is stacked with the insulator and includes a gate material layer having a first work function and a first interfacial layer. The first interfacial layer is directly between the insulator and the gate material layer, wherein the gate electrode structure has a second work function that is different from the first work function.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: An acoustic wave element includes: a substrate; a bonding structure on the substrate; a support layer on the bonding structure; a first electrode including a lower surface on the support layer; a cavity positioned between the support layer and the first electrode and exposing a lower surface of the first electrode; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer, wherein at least one of the first electrode and the second electrode includes a first layer and a second layer that the first layer has a first acoustic impedance and a first electrical impedance, the second layer has a second acoustic impedance and a second electrical impedance, wherein the first acoustic impedance is higher than the second acoustic impedance, and the second electrical impedance is lower than the first electrical impedance.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Abstract: Methods, apparatus, and systems for multi-resolution processing for video classification. A plurality of video frames of a video are obtained and a resolution for classifying each video frame of the plurality of video frames is determined by analyzing each video frame using a policy network. Based on the determined resolution, each video frame having a determined resolution is rescaled and each rescaled video frame is routed to a classifier of a backbone network that corresponds to the determined resolution. Each rescaled video frame is classified using the corresponding classifier of the backbone network to obtain a plurality of classifications and the classifications are averaged to determine an action classification of the video.

Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.

Abstract: A method and system of stitching a plurality of image views of a scene, including grouping matched points of interest in a plurality of groups, and determining a similarity transformation with smallest rotation angle for each grouping of the matched points. The method further includes generating virtual matching points on non-overlapping area of the plurality of image views and generating virtual matching points on overlapping area for each of the plurality of image views.

Abstract: A computer-implemented method for finding objects in a collection of images or video, the method comprising: assessing a similarity between two subgraphs; detecting the objects in the collection; assessing a relationship between the objects; finding attributes of the objects; constructing a collection graph for the collection where each of the objects is the vertices and nodes of the collection graph and their relationships with other objects and attributes are edges of the collection graphs; recursively identifying coherent subgraphs and turning the coherent subgraphs into new meta-nodes of the collection graph; identification of the stable graph reducing the collection graph into zero or more distinct stories; assigning a similarity score for each pair of the stories based on a similarity between the corresponding stories; linking the stories into inlier stories based on the similarity score being greater than a first pre-determined threshold level.

Abstract: Systems, computer-implemented methods, and computer program products to focus a microscope. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analyzer component that can analyze sub-images of respective sample images to identify one or more sub-images having a maximized variance of a gradient derivative corresponding to the one or more sub-images. The respective sample images can be acquired at one or more focal positions along an optical axis of a microscope. The computer executable components can further comprise a selection component that can select an image, from the respective sample images, that comprises the one or more sub-images identified. The computer executable components can also comprise a focus component that, based on a focal position corresponding to the image selected, can focus the microscope to the focal position.

Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.

Abstract: A method and system of stitching a plurality of image views of a scene, including grouping matched points of interest in a plurality of groups, and determining a similarity transformation with smallest rotation angle for each grouping of the matched points. The method further includes generating virtual matching points on non-overlapping area of the plurality of image views and generating virtual matching points on overlapping area for each of the plurality of image views.

Abstract: A system and a method for tracking a plurality of objects, including obtaining input data, estimating a number of skipping frames of the input data based on information from the input data, predicting results based on the estimating of the number of skipping frames, and correcting the predicted results.

Abstract: A method and system of stitching a plurality of image views of a scene, including grouping matched points of interest in a plurality of groups, and determining a similarity transformation with smallest rotation angle for each grouping of the matched points. The method further includes generating virtual matching points on non-overlapping area of the plurality of image views and generating virtual matching points on overlapping area for each of the plurality of image views.

Abstract: Systems, computer-implemented methods, and computer program products to focus a microscope. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analyzer component that can analyze sub-images of respective sample images to identify one or more sub-images having a maximized variance of a gradient derivative corresponding to the one or more sub-images. The respective sample images can be acquired at one or more focal positions along an optical axis of a microscope. The computer executable components can further comprise a selection component that can select an image, from the respective sample images, that comprises the one or more sub-images identified. The computer executable components can also comprise a focus component that, based on a focal position corresponding to the image selected, can focus the microscope to the focal position.

Abstract: One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.