Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: A method for manufacturing a semiconductor structure includes: forming a channel portion on a fin portion; forming two source/drain portions on the fin portion and at two opposite sides of the channel portion, in which each of the two source/drain portions includes a first semiconductor material that is doped with dopant impurities; and forming two bottom portions each of which is disposed between the fin portion and a corresponding one of the two source/drain portions, in which each of the two bottom portions includes a second semiconductor material that is different from the first semiconductor material and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the fin portion.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: A device comprises a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source/drain features are on opposite first and second sides of the gate structure, respectively. The p-type source/drain features are on opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source/drain features. The PFET channel extends within the gate structure and connects the p-type source/drain features. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: A device comprises a gate structure, n-type source/drain features, p-type source/drain features, an NFET channel, and a PFET channel. The gate structure is over a substrate. The n-type source/drain features are on opposite first and second sides of the gate structure, respectively. The p-type source/drain features are on opposite third and fourth sides of the gate structure, respectively. The NFET channel extends within the gate structure and connects the n-type source/drain features. The PFET channel extends within the gate structure and connects the p-type source/drain features. The NFET channel and the PFET channel are vertically spaced apart by the gate structure.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.