Abstract: The disclosure provides a display panel including a substrate, an active layer, a first electrode layer, a common electrode layer, a cathode layer, and a spacer. The active layer is located on the substrate. The first electrode layer is located on the active layer, and the first electrode layer includes a first gate and a second gate. The common electrode layer is located on the first electrode layer. The common electrode layer has a first region, a second region, and a first necking region. The first necking region connects the first region and the second region. The first region and the first gate are correspondingly disposed, and the second region and the second gate are correspondingly disposed. The cathode layer is located on the common electrode layer. The spacer is located between the common electrode layer and the cathode layer. The spacer and the first necking region are correspondingly disposed.

Abstract: A method of manufacturing a capacitor including the operations of etching a plurality of primary trenches into a first region of a substrate, the primary trenches extending in a first direction, etching a plurality of secondary trenches into the first region of the substrate, the secondary trenches extending in a second direction other than the first direction, with the adjacent secondary trenches and adjacent primary trenches jointly defining an island structure having an upper surface that is recessed relative to an upper surface a surrounding substrate, and depositing a series of film pairs including a dielectric layer and a conductive layer.

Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.

Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: A method to measure the transient thermal diffusivity performance of a heat dissipation module by selecting two measurement points on the surface of the heat dissipation module, and locating the two measurement points at the same side of the thermal center point but different distances, and measuring the temperature of the two measurement points separately and using first equation which is the analytical solution of the energy equation. After calculating the first equation, second and third equations are used to find M. The distance X1 between M and the first measurement point and temperature T1 at a moment of transient state are also inserted into the first equation to obtain the value of the thermal diffusivity coefficient ?, which represents the transient thermal diffusivity performance for the heat dissipation module.

Abstract: A liquid-vapor composite heat dissipation system includes a heat exchange device filled with a working fluid, a number of liquid-vapor composite heat dissipation units that are positioned higher than the heat exchange device, each of the liquid-vapor composite heat sink units having a housing with an internal capillary occupying the interior of the housing and partially separating a spatially disconnected inlet chamber and an outlet chamber. The bottom of the housing is attached to a heat source. A liquid supply tube is connected to the heat exchange device at one end, and at the other end to a liquid inlet of each of the liquid-vapor composite heat sink units through each of the liquid supply pipes. A liquid return tube is connected to the heat exchange device at one end, and to each of the liquid-vapor composite heat sink units at the other end through each of the return pipes.

Abstract: A liquid-in and vapor-out composite liquid-vapor phase conversion heat dissipation device that includes a housing with a chamber connected to an inlet and outlet; a capillary structure in the chamber for maintaining a predetermined distance from the inlet and outlet, and separating the chamber into an liquid inlet chamber and a vapor outlet chamber. The liquid inlet chamber is spatially connected to the inlet, and the vapor outlet chamber is spatially connected to the outlet. A drainage structure located at the top surface of the bottom of the housing is affixed to the bottom of the capillary structure for diverting liquid from the liquid inlet chamber to the underside of the capillary structure. The bottom surface of the bottom of the housing is affixed to a heat source, and when the heat source is attached, the drainage structure is located above the heat source.

Abstract: A fan logic evaluation device and method thereof for improving the logic evaluation of a fan. Specifically, a fan logic evaluation device is provided by first installing a fan, which corresponds to a set of parameters, in a wind tunnel device. A computer then performs a logic evaluation to convert the set of parameters into an evaluated pressure-flow curve and a measured pressure-flow curve by measuring the fan's operating conditions with the wind tunnel device. The computer further performs a logic modification to correct the logic evaluation to obtain a logic evaluation modification. The logic evaluation is then replaced by the logic evaluation modification. Finally, the above process is repeated with the same fan or a different fan.

Abstract: A method to measure the transient thermal diffusivity performance of a heat dissipation module by selecting two measurement points on the surface of the heat dissipation module, and locating the two measurement points at the same side of the thermal center point but different distances, and measuring the temperature of the two measurement points separately and using first equation which is the analytical solution of the energy equation. After calculating the first equation, second and third equations are used to find M. The distance X1 between M and the first measurement point and temperature T1 at a moment of transient state are also inserted into the first equation to obtain the value of the thermal diffusivity coefficient ?, which represents the transient thermal diffusivity performance for the heat dissipation module.

Abstract: A ventilator-weaning timing prediction system, a program product therefor, and methods for building and using the same are disclosed to help a physician to determine a timing for a ventilator-using patient to try to weaning or completely wean from mechanical ventilation using AI-based prediction.

Abstract: A thermal diffusivity performance measurement system is configured to measure a temperature of a pillar. The thermal diffusivity performance measurement system has a temperature sensor and a calculation unit. The temperature sensor is disposed at the pillar and configured to measure the temperature of the pillar. The calculation unit is configured to calculate a ratio of heat conduction to convection intensity per unit conduction intensity and a dimensionless time based on the measuring results of the temperature sensor.

Abstract: A thermal diffusivity performance measurement system is configured to measure a temperature of a pillar. The thermal diffusivity performance measurement system has a heater, a temperature sensor and a calculation unit. The heater is configured to heat the pillar. The temperature sensor is disposed at the pillar and configured to measure the temperature of the pillar. The calculation unit is connected to temperature sensor. The calculation unit is configured to calculate a ratio of heat conduction to convection intensity per unit conduction intensity and a dimensionless time based on the measuring results of the temperature sensor.

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.

Abstract: Provided herein are methods for treating or preventing Wnt-associated cancers, comprising administering an effective amount of a DNAPK inhibitor to a patient having a Wnt-associated cancer.