Abstract: An electronic device is provided, including a chip unit, a heat dissipation film, an encapsulation layer, a through hole, and a circuit structure. The chip unit has a first side and a second side opposite to the first side. The heat dissipation film is disposed on the first side. The encapsulation layer surrounds the chip unit and the heat dissipation film. The through hole penetrates the encapsulation layer, and has a first position and a second position. The circuit structure is disposed on the second side. The through hole is electrically connected to the chip unit through the circuit structure. The first position is connected to the circuit structure, and the second position is farther away from the circuit structure than the first position. The first position has a first width, the second position has a second width, and the first width is greater than the second width.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system that includes a pixel processing stage decoupled from an entropy coding stage is disclosed. The pixel processing results comprise quantized transform coefficients that are divided into component blocks. The component blocks including non-zero data are identified. An optimized version of the pixel processing results for storage in a buffer storage is generated. The optimized version includes an identification of which of the component blocks include non-zero data, and the optimized version includes contents of one or more of the component blocks that include non-zero data, without including contents of one or more of the component blocks that only include zero data. The optimized version of the pixel processing results is provided for storage in the buffer storage. The optimized version of the pixel processing results from the buffer storage is received and processed to generate an unpacked version of the pixel processing results for use in entropy coding.

Abstract: A system comprises a memory storage configured to store at least a portion of a frame of a video and a hardware motion estimation search processing unit configured to perform at least a portion of a motion estimation search for the video for a plurality of different block sizes. The hardware motion estimation search processing unit is configured to perform the motion estimation search using a plurality of source sub-blocks of a first block size to determine a first type of comparison evaluation values for the first block size. A combination of values included in the first type of comparison evaluation values is utilized to determine at least one second type of comparison evaluation values for a second block size, wherein the second block size is larger than the first block size.

Abstract: A disclosed computer-implemented method may include (1) selecting, from a video stream, a reference frame and a current frame, (2) collecting a reference histogram of the reference frame and a current histogram of the current frame, and (3) generating a smoothed reference histogram by applying a smoothing function to at least a portion of the reference histogram. In some examples, the computer-implemented method may also include (1) determining a similarity metric between the smoothed reference histogram and the current histogram and, (2) when the similarity metric is greater than a threshold value, applying weighted prediction during a motion estimation portion of an encoding of the video stream. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video. Each of the hardware motion estimation search processing units is configured to be assigned a different one of the plurality of different reference frames and is configured to compare at least the portion of the source block with a portion of the assigned one of the different reference frames.

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits.

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.

Abstract: A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups.