Patents by Inventor Chung G. Choi

Chung G. Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5504357
    Abstract: A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: April 2, 1996
    Assignee: Hyundai Electronics Industries, Co., Ltd.
    Inventors: Jong S. Kim, Hee-Koo Yoon, Chung G. Choi
  • Patent number: 5376575
    Abstract: A DRAM having a vertical transistor of a highly integrated semiconductor device and its manufacturing method are disclosed. A DRAM has a silicon substrate, a word line formed in a silicon substrate, a gate oxide layer formed on the side wall of the word line, a bit line junction region formed on the bottom of a silicon substrate, a bit line that is connected to the a bit line junction region and is insulated from the word line via a first insulating layer, a charge storage electrode junction region formed near the bottom of silicon substrate surface, a pad polysilicon layer that is insulated from the a word line via a second insulating layer and is connected at the top of a charge storage electrode diffusion region, and a charge storage electrode that is connected to the pad polysilicon layer through a contact.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: December 27, 1994
    Assignee: Hyundai Electronics Industries, Inc.
    Inventors: Jong S. Kim, Hee-Koo Yoon, Chung G. Choi
  • Patent number: 4983546
    Abstract: A method for curing spin-on-glass formed on a wafer film which insulates the metal layers and flattens any step difference in the process for manufacturing a multi-layered metal layer of a highly integrated semiconductor device which comprises establishing a predetermined initial temperature in a heating chamber with an ultraviolet light source. A wafer, on which a SOG film to be cured is formed, is then introdued into the heated chamber and the temperature gradually increased to a predetermined maximum temperature. The SOG film is irradiated with ultraviolet light at a predetermined wavelength simultaneously with the application of heat at the maximum temperature for a predetermined time. The wafer is then cooled.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: January 8, 1991
    Assignee: Hyundai Electronics Industries, Co., Ltd.
    Inventors: Il S. Hyun, Hae S. Park, Chung G. Choi, Ho G. Ryoo, Jai O. Koh, Sang I. Kim, Sung K. Park, Yung M. Koo, Young I. Kim, Sea C. Kim