Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract: A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.