Patents by Inventor Chung-Han Chou

Chung-Han Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9477258
    Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 25, 2016
    Assignees: Industrial Technology Research Institute, Chung Yuan Christian University, National Tsing Hua University
    Inventors: Yow-Tyng Nieh, Shih-Hsu Huang, Shih-Chieh Chang, Chung-Han Chou
  • Publication number: 20150026490
    Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventors: Yow-Tyng Nieh, Shih-Hsu Huang, Shih-Chieh Chang, Chung-Han Chou
  • Publication number: 20140351616
    Abstract: A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.
    Type: Application
    Filed: September 6, 2013
    Publication date: November 27, 2014
    Applicants: Industrial Technology Research Institute, Chung Yuan Christian University, National Tsing Hua Univerisity
    Inventors: Yow-Tyng Nieh, Shih-Chieh Chang, Chung-Han Chou, Shih-Hsu Huang