Patents by Inventor CHUNG-HAN HSIEH

CHUNG-HAN HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160216829
    Abstract: A method for making input devices connected to a smartphone to function as touch control to the smartphone is disclosed. The method includes the steps of: a) operatably connecting the handheld computer to a personal computer with an input device; b) presenting the input device to be a virtual touch sensitive device to the handheld computer when the input device is a non-touch sensitive device; c) converting a first touch event of the input device into a second touch event compatible to the handheld computer when the input device is a touch sensitive device and is being touched; and d) sending the second touch event to the handheld computer.
    Type: Application
    Filed: December 18, 2015
    Publication date: July 28, 2016
    Applicant: I/O INTERCONNECT, LTD.
    Inventors: Kun-Yuan Lin, Chung-Han Hsieh
  • Publication number: 20160216774
    Abstract: A method for generating operable cursor on a monitor connected to a smartphone is disclosed. The method includes the steps of: a) providing a cursor generator which receives a source video signal, outputs a generated video signal, and is also capable of connecting a mouse; b) operationally connecting the cursor generator between the monitor and the smartphone to receive the source video signal from the smartphone; c) generating a cursor into the source video signal; and d) outputting the generated video signal with the cursor to the monitor and sending a positional signal of the cursor to the smartphone.
    Type: Application
    Filed: September 23, 2015
    Publication date: July 28, 2016
    Applicant: I/O INTERCONNECT INC.
    Inventors: Ping-Shun Zeung, Chung-Han Hsieh, Szu-Wan Lu
  • Publication number: 20130049800
    Abstract: A sub-threshold voltage circuit of multi-channel length includes a plurality of logic gates, which are electrically connected with one another according to a predetermined manner and composed of a plurality of PMOS transistors and a plurality of NMOS transistors. The logic gates form a plurality of signal paths defining at least one key signal path and a plurality of general signal paths respectively. The channel lengths of the logic gates located on the general signal paths each are the minimum channel length of the manufacturing process of the transistor. The logic gate located on the at least one key signal path is an RSCE PMOS or NMOS transistor, the channel length of which is larger than the minimum channel length of the manufacturing process of the transistor to define a maximum channel length. Thus, the performance is enhanced, leakage current is less, and the circuit area keeps proper in degree.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: JINN-SHYAN WANG, CHUNG-HAN HSIEH, KENG-JUI CHANG