Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: A method for adjusting application settings is provided. The method includes using an application setting module to receive at least one performance target from an application running on an electronic device. The method further includes using the application setting module to record at least one performance indicator of the application while the application is running, wherein the performance indicator corresponds to the performance target. The method further includes using the application setting module to estimate the estimated time that the temperature of the electronic device sustains less than the defense temperature. The method further includes using the application setting module to determine the score according to the performance indicator and the estimated time, wherein the score indicates to the application that it should raise, lower, or keep a current setting.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A connecting device used for electrically connecting a power source with a power consuming module is provided. The connecting device includes a female connecting base and a male connecting base. The female connecting base has two opposite surfaces, a rim disposed on one of the surfaces and two terminals exposed on the surfaces. The terminals are connected to the live wire and neutral wire of the power source separately. The male connecting base includes a clamp, two conductive strips, and a ground strip. The rim is clamped, and the male connecting base is fastened to the female connecting base by the clamp. The terminals are connected to the conductive strips, while the end surface of each conductive strip protrudes from the surface of the male connecting base. The ground strip includes a ground surface which protrudes from the end surfaces of the conductive strips.

Abstract: A conductive rod includes an outer tube unit, at least one insulating member, and a conductive unit. The outer tube unit is made of conductive material, and has a first end and a second end, the first end and the second end are communicated with a tube space. The insulating member is disposed on the first end of the outer tube unit. One end of the conductive unit is positioned on the insulating member, and the other end of the conductive unit extends toward the second end along the tube space of the outer tube unit. The conductive unit is not in contact with the outer tube unit. The present invention also provides a lamp, comprising at least one conductive rod as described above, a lamp holder combined with a top end of the conductive rod, and a base combined with a bottom end of the conductive rod.

Abstract: EUV masks and methods of fabrication thereof are described herein. An exemplary method includes receiving an EUV mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. The method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. The first etching process uses a first etchant, and the second etching process uses a second etchant. The second etchant is different than the first etchant. In some embodiments, the first etchant is a halogen-based plasma (e.g., a Cl2 plasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a Cl2+O2 plasma).

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A memory device is formed in an interconnect structure over a substrate. Forming the memory device includes forming an alternating stack of dielectric material layers and conductive material layers, wherein the alternating stack includes a memory array region and a staircase region adjacent to the memory array region; forming a trench on the memory array region of the alternating stack; forming a data storage layer, channel layers, bit line pillars, and source line pillars in the trench; and performing patterning processes to from a staircase structure on the staircase region. The staircase structure steps downward from a first direction and makes a 180-degree turn to step downward in a second direction opposite to the first direction.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A secondary-side controller applied to a flyback power converter prevents a secondary side of the flyback power converter from conducting incorrectly. The secondary-side controller includes a first comparison circuit, a second comparison circuit, and a gate control signal generation circuit. The first comparison circuit generates a first comparison signal according to a drain voltage of a synchronous switch of the secondary side of the flyback power converter and a first parameter. The second comparison circuit generates a ready signal according to the first comparison signal and a resistance of an external resistor. The gate control signal generation circuit generates a gate control signal to the synchronous switch according the ready signal and the drain voltage, and the synchronous switch is turned on according to the gate control signal.

Abstract: The present invention relates to the use of a Raman spectral signature of nitrate, as a biomarker for an early, real-time diagnosis of nitrogen status in growing plants in a non-invasive or non-destructive way in order to detect nitrogen deficiency before the onset of any visible symptoms. The early, real-time diagnosis of nitrogen deficiency in plants makes it possible to correct nitrogen deficiency for the avoidance of negative effects on the yield and biomass of growing plants or leafy vegetables.

Abstract: A system for navigating a virtual environment using seated walking-in-place footstep locomotion includes a virtual reality device, a first sensing device, and a second sensing device. The first sensing device senses the first footstep locomotion of one of feet of a user seated in a physical environment to generate and transmit a first stepping signal to the virtual reality device. The second sensing device senses the second footstep locomotion of another of the feet of the user seated in the physical environment to generate and transmit a second stepping signal to the virtual reality device. The virtual reality device navigates the virtual environment in a virtual locomotion mode based on a combination of the first stepping signal and the second stepping signal.

Abstract: Disclosed is the source active region.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: The present invention relates to the use of a Raman spectral signature of nitrate, as a biomarker for an early, real-time diagnosis of nitrogen status in growing plants in a non-invasive or non-destructive way in order to detect nitrogen deficiency before the onset of any visible symptoms. The early, real-time diagnosis of nitrogen deficiency in plants makes it possible to correct nitrogen deficiency for the avoidance of negative effects on the yield and biomass of growing plants or leafy vegetables.

Abstract: Described herein are modular server systems. The server systems include a server chassis having one or more window bays each having the same dimensions. The system also includes a plurality of device trays each for holding a device that is selected from a plurality of different devices. Each device tray fits in the one or more window bays.