Abstract: The present disclosure provides systems and methods for controlling a semiconductor manufacturing apparatus. A control system includes an inspection unit capturing a set of images of the semiconductor manufacturing apparatus, a sensor interface receiving the set of images and generating at least one input signal for a database server, and a control unit. The control unit includes a front end subsystem, a calculation subsystem, and a message and feedback subsystem. The calculation subsystem receives the data signal from the front end subsystem, wherein the calculation subsystem performs an artificial intelligence analytical process to determine, according to the data signal, whether a malfunction has occurred in the semiconductor manufacturing apparatus and to generate an output signal. The message and feedback subsystem generates an alert signal and a feedback signal according to the output signal, and the alert signal is transmitted to a user of the semiconductor manufacturing apparatus.

Abstract: The present disclosure provides systems and methods for controlling a semiconductor manufacturing apparatus. A control system includes an inspection unit capturing a set of images of the semiconductor manufacturing apparatus, a sensor interface receiving the set of images and generating at least one input signal for a database server, and a control unit. The control unit includes a front end subsystem, a calculation subsystem, and a message and feedback subsystem. The calculation subsystem receives the data signal from the front end subsystem, wherein the calculation subsystem performs an artificial intelligence analytical process to determine, according to the data signal, whether a malfunction has occurred in the semiconductor manufacturing apparatus and to generate an output signal. The message and feedback subsystem generates an alert signal and a feedback signal according to the output signal, and the alert signal is transmitted to a user of the semiconductor manufacturing apparatus.

Abstract: A system and method for upgrading data transmission performance under programmed input/output (PIO) mode is disclosed. In one embodiment, a PIO accelerating device is established in an IDE controller for handling data transmissions concerned with read/write operations after taking over associated control right from processing unit. A counter is configured in the PIO accelerating device for varying its stored content followed by a predetermined sequence in responsive to the input pulses of a system clock. A timing signal generator is also established in the PIO accelerating device for issuing signals directed to the IDE device and the buffer in the IDE controller for activating associated data transmission operations while the stored content reaches to a predetermined threshold. Optimal performance to data transmission under IO mode 4 of the PIO mode can be achieved by employing the disclosed hardware configuration.

Abstract: A method and an apparatus of loading a pre-load seed for a test code of a physical layer device (PHY). For a physical layer device including a scrambler and a Non-Return-to-Zero/Non-Return-to-Zero-Inverted (NRZ/NRZI) converter connected to the scrambler, where the NRZ/NRZI converter receives an NRZ signal outputted by the scrambler, and outputs an NRZI signal, the method includes the following steps. (a) Determine whether a plurality of starting bits of a frame are present. (b) Repeat from step (a) if the starting bits are not present. (c) Load the pre-load seed to the scrambler and transmitting the test code. (d) Set the NRZI signal in a high level when the NRZI signal is not in the high level. On the other hand, for a physical layer device having a descrambler, the method includes the steps of: (a) determining whether a plurality of starting bits of a frame are present; and (b) loading the pre-load seed to the descrambler to retrieve the test code.

Abstract: A system and method for upgrading data transmission performance under programmed input/output (PIO) mode is disclosed. In one embodiment, a PIO accelerating device is established in an IDE controller for handling data transmissions concerned with read/write operations after taking over associated control right from processing unit. A counter is configured in the PIO accelerating device for varying its stored content followed by a predetermined sequence in responsive to the input pulses of a system clock. A timing signal generator is also established in the PIO accelerating device for issuing signals directed to the IDE device and the buffer in the IDE controller for activating associated data transmission operations while the stored content reaches to a predetermined threshold. Optimal performance to data transmission under IO mode 4 of the PIO mode can be achieved by employing the disclosed hardware configuration.

Abstract: A method and an apparatus of loading a pre-load seed for a test code of a physical layer device (PHY). For a physical layer device including a scrambler and a Non-Return-to-Zero/Non-Return-to-Zero-Inverted (NRZ/NRZI) converter connected to the scrambler, where the NRZ/NRZI converter receives an NRZ signal outputted by the scrambler, and outputs an NRZI signal, the method includes the following steps. (a) Determine whether a plurality of starting bits of a frame are present. (b) Repeat from step (a) if the starting bits are not present. (c) Load the pre-load seed to the scrambler and transmitting the test code. (d) Set the NRZI signal in a high level when the NRZI signal is not in the high level. On the other hand, for a physical layer device having a descrambler, the method includes the steps of: (a) determining whether a plurality of starting bits of a frame are present; and (b) loading the pre-load seed to the descrambler to retrieve the test code.

Abstract: A method and system for compressing graphic data by dividing the data into segments is disclosed. The size of the divided segment is programmable. A frame buffer partitioned into a compressed frame buffer and an uncompressed frame buffer stores graphic data. Each segment of the graphic data is compressed by three different algorithms that encode the graphic data as a plurality of code-words. Each code-word for the segment is taken from the algorithm that can compress the largest number of pixels in the code-word. A header is used to indicate the number of code-words and the compression method used in each code-word. The total number of bytes obtained from the compression of a segment is compared to a pre-defined limit to determine if the compression of the segment is successful. The successfully compressed data of a segment are written to the compressed frame buffer. A compression status flag buffer is used to identify if a segment is compressed or not.