Abstract: A memory device includes a substrate, a first cell string, second cell string, and third cell string, each connected to a first bit line and formed in a direction perpendicular to a top surface of the substrate, a first upper ground selection line connected to the first cell string, a second upper ground selection line separated from the first upper ground selection line and connected to the second and third cell strings, a first lower ground selection line connected to the first and second cell strings, and a second lower ground selection line separated from the first lower ground selection line and connected to the third cell string.

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Abstract: A semiconductor device includes; a first transistor on a substrate and including a first gate electrode, a second transistor on the substrate and including a second gate electrode adjacent to the first gate electrode, an electrode structure including electrodes vertically stacked on the first and second transistors and including first and second pads adjacent to in the first direction, first and second landing pads between the substrate and the electrode structure connected respectively to the first and second landing pads, a first penetration electrode penetrating the electrode structure to connect the first landing pad and the first pad, a second penetration electrode penetrating the electrode structure to connect the second landing pad and the second pad, and lower interconnection lines between the first landing pad and the second landing pad and extending in a second direction substantially perpendicular to the first direction.

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.

Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.

Abstract: A variable voltage generation circuit includes a first amplification circuit and a second amplification circuit. The first amplification circuit generates a first output voltage based on a reference voltage, a first feedback voltage, a temperature-varied voltage and a temperature-fixed voltage such that the first output voltage is varied in a first voltage range according to a variation of the operational temperature. The first amplification circuit generates the first feedback voltage based on the first output voltage. The second amplification circuit generates a second output voltage based on the first feedback voltage, a second feedback voltage, the temperature-varied voltage and the temperature-fixed voltage such that the second output voltage is varied in a second voltage range wider than the first voltage range according to the variation of the operational temperature. The second amplification circuit generates the second feedback voltage based on the second output voltage.

Abstract: A variable voltage generation circuit includes a first amplification circuit and a second amplification circuit. The first amplification circuit generates a first output voltage based on a reference voltage, a first feedback voltage, a temperature-varied voltage and a temperature-fixed voltage such that the first output voltage is varied in a first voltage range according to a variation of the operational temperature. The first amplification circuit generates the first feedback voltage based on the first output voltage. The second amplification circuit generates a second output voltage based on the first feedback voltage, a second feedback voltage, the temperature-varied voltage and the temperature-fixed voltage such that the second output voltage is varied in a second voltage range wider than the first voltage range according to the variation of the operational temperature. The second amplification circuit generates the second feedback voltage based on the second output voltage.