Patents by Inventor Chung-Hsi Liu

Chung-Hsi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847962
    Abstract: The present invention provides an active mini LED display and driving method thereof. The driving method comprises: controlling a gate voltage of the metal oxide field effect transistor by a voltage to modulate the current and luminous brightness required to driver the light emitting diode; processing display data to generate timing-controlled channel signals and scanning signals to driver transistors and light emitting diodes to achieve image display; modulating scanning voltage signals or channel voltage signals into analog-type voltages and/or pulse-width-type voltages, and then compensating the unevenness in brightness produced by the epitaxy of each light-emitting diode. The driving method of the active mini LED display of the present invention can reduce the power loss of transmission, and can integrate with various light emitting diodes within a small pixel pitch to manufacture various displays by means of heterogeneous polycrystalline wafer-level packaging.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: December 19, 2023
    Inventors: Tai-Hui Liu, Chung-Hsi Liu
  • Patent number: 11476242
    Abstract: The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 18, 2022
    Assignee: ULTRABAND TECHNOLOGIES INC.
    Inventors: Tai-Hui Liu, Chung-Hsi Liu
  • Publication number: 20210358899
    Abstract: The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.
    Type: Application
    Filed: April 14, 2021
    Publication date: November 18, 2021
    Inventors: Tai-Hui Liu, Chung-Hsi Liu