Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.

Abstract: An information delivery method for transferring fund is provided. The information delivery method includes receiving payment information, determining whether a transfer condition is met according to the payment information, in response to determining that the transfer condition is met, obtaining source account information of a source entity and destination account information of a destination entity in the payment information, determining a transfer path according to the source account information of the source entity and the destination account information of the destination entity, and transmitting the payment information from the source entity to the destination entity according to the transfer path.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a substrate, an antenna, and an active component. The antenna is disposed at least partially within the substrate. The active component is disposed on the substrate and electrically connected to the antenna. A location of the antenna is configured to be adjustable with respect to a location of the active component.

Abstract: A portable ring-type fluorescence optical system for observing microfluidic channel and an operating method thereof are disclosed. The portable ring-type fluorescence optical system includes a photographic chip, a first polarizer, an objective lens, a ring-type fluorescent light source, a biological sample on a microfluidic chip, a second polarizer and a bottom illumination light source arranged in order from top to bottom. The ring-type fluorescent light source is used to generate a ring-type fluorescent light to the biological sample on the microfluidic chip. The objective lens is used to magnify a fluorescent image of the biological sample on the microfluidic chip to focus on the photographic chip. The first polarizer disposed under the photographic chip and the second polarizer disposed under the biological sample form a non-zero angle to each other to block reflected lights that the biological sample reflects the lights emitted by the bottom illumination light source.

Abstract: A carbon dioxide and exhaust gas capture device that is a device being unique in the world and being able to truly suppress carbon dioxide is provides and has a cold water tank set, a photosynthetic tank set, and a terrestrial plant tank set. The cold water tank set reduces temperature of exhaust gas and filters toxic gases and pollutant particles. The photosynthetic tank set and the terrestrial plant tank set further photosynthesize the exhaust gas with organisms that derive energy from photosynthesis and terrestrial plants to produce oxygen. Moreover, the carbon dioxide and exhaust gas capture device requires low cost, has high efficiency, produces zero pollution during the process, has a long service life, and has high added value.

Abstract: A system for determining an assessment of at least one exercise performed by a user is described. The system includes an input device, and a computing device. The input device is configured to monitor at least one exercise performed by a user. The computing device includes processors and a memory. The memory is coupled to the processors and stores program instructions that when executed by the processors cause the processors to: (1) generate a user interface displaying a content; (2) provide an instruction associated with the at least one exercise; (3) determine an indication of movement associated with the at least one exercise; (4) in response to a determination of the indication of movement, determine an assessment of the at least one exercise; and (5) in response to a determination of the assessment of the at least one exercise, perform an operation.

Abstract: A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: The instant disclosure described a system and method to prevent the oxidizer overheating using cold side bypass for a VOCs treatment system with series rotor, which may be used in an organic waste air treatment system. The system is equipped with a Thermal Oxidizer (TO), a First Heat Exchanger, a Second Heat Exchanger, a third heat exchanger, a First Cold-Side Transporting Pipeline, a First Adsorption Rotor, a Second Adsorption Rotor, and a Chimney. There is a Cold-Side Proportional Damper installed between the First Desorption-Treated Air Pipeline and the First Cold-Side Transporting Pipeline, or it is installed on the First Desorption-Treated Air Pipeline. When the VOCs concentration becomes higher, the Cold-Side Proportional Damper can regulate the airflow to adjust the heat-recovery amount or concentration, when treating the organic waste air, it can prevent the TO from being overheated due to high oxidizer temperature, and protect it from Thermal Oxidizer shut-down.

Abstract: A system and method to prevent the oxidizer overheating using cold side bypass during high input for a VOCs treatment system with series rotor are described, which may be used in an organic waste air treatment system. The system is equipped with a Thermal Oxidizer (TO), a First Heat Exchanger, a Second Heat Exchanger, a third heat exchanger, a Fourth Heat Exchanger, a First Cold-Side Transporting Pipeline, a Fourth Cold-Side Transporting Pipeline, a First Adsorption Rotor, a Second Adsorption Rotor, and a Chimney. There is a Cold-Side Proportional Damper installed between the First Desorption-Treated Air Pipeline and the First Cold-Side Transporting Pipeline, the First Desorption-Treated Air Pipeline and the Fourth Cold-Side Transporting Pipeline or between the First Cold-Side Transporting Pipeline and the Fourth Cold-Side Transporting Pipeline, or the damper is installed on the First Desorption-Treated Air Pipeline.

Abstract: An electro-acoustic product stabilizing device includes: a sound device; an angle adjustment element, coupled pivotally to one side of the sound device; a hard fixation portion, configured on one side of the angle adjustment element; and a flexible support element, in connection with the angle adjustment element. Whereby, when the electro-acoustic product of the present invention is a headset or hearing aid, it is attached and fixed in a user's ear through the characteristic of the flexible support element being capable of adaptable shape change to be fixed to the use's inner ear bones; and then, the attachment of the flexible support element to the ear to be more comfortable through the angle adjustment element in combination with the sound device. In addition, the strengthening fixation of the hard fixation portion to the sound device increases the combination stability of the sound device with the ear.

Abstract: The earpiece structure includes a main member having a sound releasing element on an inner side, a fixation element besides the sound releasing element slant toward an outer side of the main member, and an extension element between the sound releasing element and the fixation element. A number of through opening are configured on the extension element, each configured with a tuning element. A speaker element is disposed on the fixation element. Due to the slant arrangement of the fixation element, the sound wave from the speaker element progresses directly towards a user's eardrum through the ear canal. The tuning elements achieve an optimal proportion between air pressures of front and rear chambers of the earpiece structure, allowing the sound wave to reverberate and reflect in a sound space and achieving superior sound field.

Abstract: A scroll type air compressor provided by the invention utilizes an L-shape mounting frame for respectively mounting a compressor and a generator to a first mounting section and a second mounting section thereon. The generator is mounted to the second mounting section via a plate and is capable of being fine-tuned in displacement with respect to the plate, such that a second end surface of a second drive pulley of the generator can be made coplanar with a first end surface of a first drive pulley of the compressor. The position of the plate can also be adjusted up and down with respect to the second mounting section to a required position so that the distance between the drive pulleys of the generator and the compressor can be adjusted and the tension of a transmission belt can be determined.

Abstract: A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.

Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.

Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.