Patents by Inventor Chung-Hsien Chen

Chung-Hsien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180295437
    Abstract: An electro-acoustic product stabilizing device includes: a sound device; an angle adjustment element, coupled pivotally to one side of the sound device; a hard fixation portion, configured on one side of the angle adjustment element; and a flexible support element, in connection with the angle adjustment element. Whereby, when the electro-acoustic product of the present invention is a headset or hearing aid, it is attached and fixed in a user's ear through the characteristic of the flexible support element being capable of adaptable shape change to be fixed to the use's inner ear bones; and then, the attachment of the flexible support element to the ear to be more comfortable through the angle adjustment element in combination with the sound device. In addition, the strengthening fixation of the hard fixation portion to the sound device increases the combination stability of the sound device with the ear.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 11, 2018
    Inventor: Chung-Hsien CHEN
  • Publication number: 20180234753
    Abstract: The earpiece structure includes a main member having a sound releasing element on an inner side, a fixation element besides the sound releasing element slant toward an outer side of the main member, and an extension element between the sound releasing element and the fixation element. A number of through opening are configured on the extension element, each configured with a tuning element. A speaker element is disposed on the fixation element. Due to the slant arrangement of the fixation element, the sound wave from the speaker element progresses directly towards a user's eardrum through the ear canal. The tuning elements achieve an optimal proportion between air pressures of front and rear chambers of the earpiece structure, allowing the sound wave to reverberate and reflect in a sound space and achieving superior sound field.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 16, 2018
    Inventor: CHUNG-HSIEN CHEN
  • Publication number: 20170335850
    Abstract: A scroll type air compressor provided by the invention utilizes an L-shape mounting frame for respectively mounting a compressor and a generator to a first mounting section and a second mounting section thereon. The generator is mounted to the second mounting section via a plate and is capable of being fine-tuned in displacement with respect to the plate, such that a second end surface of a second drive pulley of the generator can be made coplanar with a first end surface of a first drive pulley of the compressor. The position of the plate can also be adjusted up and down with respect to the second mounting section to a required position so that the distance between the drive pulleys of the generator and the compressor can be adjusted and the tension of a transmission belt can be determined.
    Type: Application
    Filed: December 28, 2016
    Publication date: November 23, 2017
    Inventors: Yi-Chao Huang, Jou-Chien Chen, Chung-Hsien Chen, Yun-Kai Chang
  • Patent number: 9634001
    Abstract: A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 9536772
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu
  • Patent number: 9379108
    Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 9236253
    Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Chen, Ting-Chu Ko, Chih-Hao Chang, Chih-Sheng Chang, Shou-Zen Chang, Clement Hsingjen Wann
  • Publication number: 20150311111
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Application
    Filed: July 7, 2015
    Publication date: October 29, 2015
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu
  • Publication number: 20150236016
    Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 9093531
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu
  • Patent number: 9087903
    Abstract: A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu
  • Patent number: 9048317
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 8963251
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a fin structure disposed over the substrate in the gate region. The fin structure includes a first semiconductor material layer as a lower portion of the fin structure, a semiconductor oxide layer as a middle portion of the fin structure and a second semiconductor material layer as an upper portion of the fin structure. The semiconductor device also includes a dielectric feature disposed between two adjacent fin structures over the substrate. A top surface of the dielectric feature located, in a horizontal level, higher than the semiconductor oxide layer with a distance d. The semiconductor device also includes a high-k (HK)/metal gate (MG) stack disposed in the gate region, including wrapping over a portion of the fin structure.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Yu-Lien Huang, Chung-Hsien Chen, Chi-Wen Liu
  • Publication number: 20150035017
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Publication number: 20140367800
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a fin structure disposed over the substrate in the gate region. The fin structure includes a first semiconductor material layer as a lower portion of the fin structure, a semiconductor oxide layer as a middle portion of the fin structure and a second semiconductor material layer as an upper portion of the fin structure. The semiconductor device also includes a dielectric feature disposed between two adjacent fin structures over the substrate. A top surface of the dielectric feature located, in a horizontal level, higher than the semiconductor oxide layer with a distance d. The semiconductor device also includes a high-k (HK)/metal gate (MG) stack disposed in the gate region, including wrapping over a portion of the fin structure.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Tung Ying Lee, Yu-Lien Huang, Chung-Hsien Chen, Chi-Wen Liu
  • Publication number: 20140361336
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu
  • Publication number: 20140332904
    Abstract: A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 13, 2014
    Inventors: Clement Hsingjen WANN, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH, Ting-Chu KO, Chung-Hsien CHEN
  • Publication number: 20140319462
    Abstract: A device comprises insulation regions disposed in a substrate and a semiconductor fin extending above top surfaces of the insulation regions. The semiconductor fin comprises a first material. A semiconductor region comprising a second material extends from a first side of the semiconductor fin over a top of the fin to a second side of the fin. A strain buffer layer is disposed between, and contacts, the semiconductor fin and the semiconductor region. The strain buffer layer comprises an oxide, and a bottommost surface of the strain buffer layer is vertically spaced apart from the top surfaces of the insulation regions.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 30, 2014
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu
  • Patent number: 8816444
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 8796666
    Abstract: A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu