Patents by Inventor Chung-Hsien Hua
Chung-Hsien Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9093126Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.Type: GrantFiled: July 31, 2012Date of Patent: July 28, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin Yang, Kao-Cheng Lin, Chung-Hsien Hua
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Patent number: 8988949Abstract: One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.Type: GrantFiled: October 2, 2012Date of Patent: March 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chung-Hsien Hua, Chung-Yi Wu, Chen-Lin Yang, Cheng Hung Lee
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Patent number: 8848467Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.Type: GrantFiled: April 30, 2013Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsien Hua, Yu-Hao Hsu, Chen-Li Yang, Cheng Hung Lee
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Publication number: 20140269115Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.Type: ApplicationFiled: April 30, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Chung-Hsien Hua, Yu-Hao Hsu, Chen-Lin Yang, Cheng Hung Lee
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Patent number: 8830784Abstract: A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.Type: GrantFiled: October 14, 2011Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Lin Yang, Wei Min Chan, Chung-Hsien Hua
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Publication number: 20140092695Abstract: One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chung-Hsien Hua, Chung-Yi Wu, Chen-Lin Yang, Cheng Hung Lee
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Publication number: 20140036580Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin YANG, Kao-Cheng LIN, Chung-Hsien HUA
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Publication number: 20130094308Abstract: A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Lin Yang, Wei Min Chan, Chung-Hsien Hua
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Patent number: 7714636Abstract: A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit.Type: GrantFiled: May 30, 2008Date of Patent: May 11, 2010Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Chien-Yi Chang, Chung-Hsien Hua
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Publication number: 20090134936Abstract: A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit.Type: ApplicationFiled: May 30, 2008Publication date: May 28, 2009Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: Chien-Yi Chang, Chung-Hsien Hua
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Patent number: 7358768Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.Type: GrantFiled: January 10, 2006Date of Patent: April 15, 2008Assignee: National Chiao Tung UniversityInventors: Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
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Publication number: 20070103885Abstract: The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed.Type: ApplicationFiled: January 10, 2006Publication date: May 10, 2007Inventors: Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
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Patent number: 7190187Abstract: The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.Type: GrantFiled: May 3, 2005Date of Patent: March 13, 2007Assignee: National Chiao Tung UniversityInventors: Chung-Hsien Hua, Wei Hwang
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Publication number: 20060119393Abstract: The present invention provides a power gating structure having data retention and intermediate modes and able to operate under multiple modes. A conventional power gating structure has only turn-on and turn-off functions, and is used to suppress a leakage current problem which has become more and more serious in advance manufacture processes, under a turn-off mode. However, in a memory circuit, such as latch, register and SRAM, when the power gate is turned off, a new power gating structure is required for data retention. The power gating structure of the present invention can be set into one of 4 different operational modes: a data retention mode for maintaining the static noise margin of the memory, an intermediate mode for reducing the interference on ground and power levels, an active mode used when the circuit operates in normal condition, and a standby mode used when the circuit does not operate.Type: ApplicationFiled: May 3, 2005Publication date: June 8, 2006Inventors: Chung-Hsien Hua, Wei Hwang