Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are provided. The method of forming the semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

Abstract: This application provides a server and a debugging method therefor. The debugging method for a server includes receiving, by a complex programmable logic device (CPLD), a control signal generated by a switching member, and generating a switching signal; and switching, by a bus switch, a communication connection of a communications port to a debug port or a Serial Over LAN port of a baseboard management controller (BMC) based on the switching signal. In this way, debugging work is completed or industrial control application information is received at the communications port.

Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: This application provides a server and a debugging method therefor. The debugging method for a server includes receiving, by a complex programmable logic device (CPLD), a control signal generated by a switching member, and generating a switching signal; and switching, by a bus switch, a communication connection of a communications port to a debug port or a Serial Over Lan port of a baseboard management controller (BMC) based on the switching signal. In this way, debugging work is completed or industrial control application information is received at the communications port.

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.

Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.