Patents by Inventor Chung-hsing Kuo

Chung-hsing Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015023
    Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Chung-Hsing Kuo, Chun-Ting Yeh, Chuan-Lan Lin, Yu-Ping Wang, Yu-Chun Chen
  • Patent number: 12148723
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: November 19, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Publication number: 20240371695
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.
    Type: Application
    Filed: June 1, 2023
    Publication date: November 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo
  • Publication number: 20240315095
    Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Yi-Feng Hsu
  • Publication number: 20240097239
    Abstract: Exemplary traction battery pack designs for use in electrified vehicles may include a thermal insulating joint configured to isolate a heat transfer path at one or more structural connections between an enclosure tray and a battery internal structure (e.g., heat exchanger plate, cross member, etc.) of the traction battery pack. The thermal insulating joint may include a first thermal insulation component and a second thermal insulation component disposed on opposite sides of the battery internal structure. The thermal insulation components cooperate to block the heat transfer path across the structural connection, thereby insulating the battery internals from an ambient surrounding of the traction battery pack.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Chung-Hsing KUO, Yongcai WANG
  • Patent number: 11912123
    Abstract: A traction battery pack venting system includes a plurality of battery arrays within a traction battery pack. The battery arrays each have a plurality of individual battery cells. The system further includes a divider system that provides a plurality of vented gas receiving compartments. Each of the vented gas receiving compartments are separate and distinct from the other vented gas receiving compartments within the plurality of vented gas receiving compartments. Each of the vented gas receiving compartments are associated with one of the battery arrays. Each of the vented gas receiving compartments can be associated with a manifold. The vent gas produced from thermal runaway can be discharged to the vented gas receiving compartments, directed to a manifold, and discharge to the external atmosphere.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 27, 2024
    Assignee: Ford Global Technologies, LLC
    Inventors: Chung-Hsing Kuo, Yongcai Wang, LeeAnn Wang, Che-chun Chang
  • Publication number: 20230238647
    Abstract: Traction battery pack designs for use in electrified vehicles may include a vent management system adapted for managing battery cell vent byproducts during battery thermal events. The vent management system includes a multi-layered structure, with each layer of the structure having a unique function related to mitigating thermal propagation. The combined functions of the vent management system may include but are not limited to guiding vent byproducts along a desired path and direction, reducing the internal volume of the traction battery pack, and absorbing/trapping solid particles of the vent byproducts.
    Type: Application
    Filed: January 21, 2022
    Publication date: July 27, 2023
    Inventors: Chung-Hsing KUO, Yongcai WANG, LeeAnn WANG, Che-chun CHANG
  • Publication number: 20230173901
    Abstract: A traction battery pack venting system includes a plurality of battery arrays within a traction battery pack. The battery arrays each have a plurality of individual battery cells. The system further includes a divider system that provides a plurality of vented gas receiving compartments. Each of the vented gas receiving compartments are separate and distinct from the other vented gas receiving compartments within the plurality of vented gas receiving compartments. Each of the vented gas receiving compartments are associated with one of the battery arrays. Each of the vented gas receiving compartments can be associated with a manifold. The vent gas produced from thermal runaway can be discharged to the vented gas receiving compartments, directed to a manifold, and discharge to the external atmosphere.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Chung-hsing Kuo, Yongcai Wang, LeeAnn Wang, Che-chun Chang
  • Publication number: 20230101900
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Patent number: 11569188
    Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 31, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin
  • Patent number: 11557558
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Publication number: 20220415836
    Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.
    Type: Application
    Filed: July 28, 2021
    Publication date: December 29, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin
  • Publication number: 20220384376
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.
    Type: Application
    Filed: August 4, 2022
    Publication date: December 1, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
  • Patent number: 11450633
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
  • Publication number: 20220005775
    Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.
    Type: Application
    Filed: August 4, 2020
    Publication date: January 6, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
  • Patent number: 11164822
    Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Hui-Ling Chen, Chien-Ming Lai
  • Publication number: 20210202418
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.
    Type: Application
    Filed: February 4, 2020
    Publication date: July 1, 2021
    Applicant: United Microelectronics Corp.
    Inventors: MING-TSE LIN, Chung-Hsing Kuo, Hui-Ling Chen
  • Patent number: 10446887
    Abstract: A battery pack includes a battery cell, a thermal interface material adjacent the battery cell and a heater element integrated with the thermal interface material.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 15, 2019
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Neil Robert Burrows, Steve F. Chorian, George Albert Garfinkel, Dhanunjay Vejalla, Chung-hsing Kuo
  • Patent number: 10333118
    Abstract: A battery pack according to an exemplary aspect of the present disclosure includes, among other things, an electronics module and an electronics umbrella positioned to channel moisture away from the electronics module.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: June 25, 2019
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Eid Farha, Hari Addanki, Keith Kearney, Chung-hsing Kuo
  • Patent number: 10199697
    Abstract: An exemplary battery pack includes a battery assembly and an enclosure assembly housing the battery assembly. The enclosure assembly is arranged to dissipate heat from at least two sides of the battery assembly.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: February 5, 2019
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Hari Addanki, Steve F. Chorian, George Albert Garfinkel, Keith Kearney, Kevin A. Montgomery, Chi Paik, Chung-hsing Kuo, Jeffrey Matthew Haag